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SN74AUC1G74YZPR Arkusz danych(PDF) 1 Page - Texas Instruments |
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SN74AUC1G74YZPR Arkusz danych(HTML) 1 Page - Texas Instruments |
1 / 12 page www.ti.com FEATURES CLR 3 2 5 8 1 CLK VCC D GND DCT PACKAGE (TOP VIEW) YEP OR YZP PACKAGE (BOTTOM VIEW) DCU PACKAGE (TOP VIEW) 3 2 4 5 1 CLK VCC PRE D GND D GND VCC Q Q See mechanical drawings for dimensions. 2 5 3 4 8 Q CLR Q Q PRE Q 4 6 7 6 7 8 6 1 7 CLK CLR PRE DESCRIPTION/ORDERING INFORMATION SN74AUC1G74 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCES537A – DECEMBER 2003 – REVISED AUGUST 2005 • Available in the Texas Instruments • Low Power Consumption, 10- µA Max I CC NanoStar™ and NanoFree™ Packages • ±8-mA Output Drive at 1.8 V • Optimized for 1.8-V Operation and Is 3.6-V I/O • Latch-Up Performance Exceeds 100 mA Per Tolerant to Support Mixed-Mode Signal JESD 78, Class II Operation • ESD Protection Exceeds JESD 22 • I off Supports Partial-Power-Down Mode – 2000-V Human-Body Model (A114-A) Operation – 200-V Machine Model (A115-A) • Sub-1-V Operable – 1000-V Charged-Device Model (C101) • Max t pd of 1.5 ns at 1.8 V This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop for higher frequencies, the CLR input overrides the PRE input when they are both low. NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. ORDERING INFORMATION TA PACKAGE(1) ORDERABLE PART NUMBER TOP-SIDE MARKING(2) NanoStar™ – WCSP (DSBGA) Tape and reel SN74AUC1G74YEPR 0.23-mm Large Bump – YEP _ _ _UP_ NanoFree™ – WCSP (DSBGA) Tape and reel SN74AUC1G74YZPR –40 °C to 85°C 0.23-mm Large Bump – YZP (Pb-free) SSOP – DCT Tape and reel SN74AUC1G74DCTR U74_ _ _ VSSOP – DCU Tape and reel SN74AUC1G74DCUR UP_ (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. (2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site. DCU: The actual top-side marking has one additional character that designates the assembly/test site. YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar, NanoFree are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright © 2003–2005, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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