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SM5168CX Arkusz danych(PDF) 6 Page - Nippon Precision Circuits Inc |
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SM5168CX Arkusz danych(HTML) 6 Page - Nippon Precision Circuits Inc |
6 / 9 page SM5168 series SEIKO NPC CORPORATION —6 FUNCTIONAL DESCRIPTION SM5168A × series Frequency dividers The comparator frequency divider (N-counter) and reference frequency divider (R-counter), one of each, are set in master-slice to the following values. I Comparator frequency divider (N-counter) = 272 to 65535 I Reference frequency divider (R-counter) = 5 to 65535 Standby mode When OPR goes from HIGH to LOW, the PLL is in standby mode with the following input/output conditions. When OPR goes from LOW to HIGH, standby mode is released and the PLL is in operating mode, and the fol- lowing start-up sequence is executed. Block State Input FIN LOW level Comparator frequency divider (N-counter) Stopped Input XIN LOW level Reference frequency divider (R-counter) Stopped Phase comparator Reset Output DO Floating Output LD LOW-level Internal feedback resistance is connected to XIN to activate the reference frequency divider (R-counter). Internal feedback resistance is connected to FIN. The comparator frequency divider (N-counter) and the phase comparator are reset. DO is floating and LD is LOW. ↓ Reference frequency divider (R-counter) starts to perform frequency division. An internal signal (FR signal) is output on the 2nd clock cycle. ↓ Phase comparator starts and comparator frequency divider (N-counter) starts to perform frequency division. DO floating condition is released and LD goes HIGH. |
Podobny numer części - SM5168CX |
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