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TS4270CM550 Arkusz danych(PDF) 4 Page - Taiwan Semiconductor Company, Ltd |
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TS4270CM550 Arkusz danych(HTML) 4 Page - Taiwan Semiconductor Company, Ltd |
4 / 9 page Preliminary TS4270 5V Ultra Low Dropout Fixed Voltage Regulator 4/9 Version: A07 Reset Timing The power-on reset delay time is defined by the charging time of an external capacitor CD which can be calculated as follows: CD = (Δt x ID,C) / ΔV CD = Delay capacitors Definitions: Δt = Reset delay Time trd ID,C = Charge current, typical 14uA ΔV = VDU, typical 1.8V VDU = Upper reset timing threshold at CD for reset delay time trd = ΔV x CD/ID,C The reset reaction time trr is the time it takes the voltage regulator to set the reset out LOW after the output voltage has dropped below the reset threshold. It is typical 1uS for delay capacitor of 47nF. For other values for CD the reaction time can be estimated using the following equation: trr ≈ 20s/F x CD Test Circuit Application Circuit |
Podobny numer części - TS4270CM550 |
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Podobny opis - TS4270CM550 |
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