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SN74LVCH245ARGYRG4 Arkusz danych(PDF) 1 Page - Texas Instruments

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Numer części SN74LVCH245ARGYRG4
Szczegółowy opis  OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
Download  27 Pages
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Producent  TI [Texas Instruments]
Strona internetowa  http://www.ti.com
Logo TI - Texas Instruments

SN74LVCH245ARGYRG4 Arkusz danych(HTML) 1 Page - Texas Instruments

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FEATURES
SN74LVCH245A . . . RGY PACKAGE
(TOP VIEW)
1
20
10
11
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
OE
B1
B2
B3
B4
B5
B6
B7
A1
A2
A3
A4
A5
A6
A7
A8
SN54LVCH245A . . . J OR W PACKAGE
SN74LVCH245A . . . DB, DGV, DW, NS,
OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
VCC
OE
B1
B2
B3
B4
B5
B6
B7
B8
SN54LVCH245A . . . FK PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
B1
B2
B3
B4
B5
A3
A4
A5
A6
A7
DESCRIPTION/ORDERING INFORMATION
SN54LVCH245A, SN74LVCH245A
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES008O – JULY 1995 – REVISED DECEMBER 2005
Operate From 1.65 V to 3.6 V
I
off Supports Partial-Power-Down Mode
Operation
Inputs Accept Voltages to 5.5 V
Bus Hold on Data Inputs Eliminates the Need
Max t
pd of 6.3 ns at 3.3 V
for External Pullup/Pulldown Resistors
Typical V
OLP (Output Ground Bounce)
Latch-Up Performance Exceeds 250 mA Per
<0.8 V at V
CC = 3.3 V, TA = 25°C
JESD 17
Typical V
OHV (Output VOH Undershoot)
ESD Protection Exceeds JESD 22
>2 V at V
CC = 3.3 V, TA = 25°C
– 2000-V Human-Body Model (A114-A)
Support Mixed-Mode Signal Operation on All
Ports (5-V Input/Output Voltage With
– 200-V Machine Model (A115-A)
3.3-V V
CC)
The SN54LVCH245A octal bus transceiver is designed for 2.7-V to 3.6-V VCC operation, and the
SN74LVCH245A octal bus transceiver is designed for 1.65-V to 3.6-V VCC operation.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
These devices are designed for asynchronous communication between data buses. These devices transmit data
from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control
(DIR) input. The output-enable (OE) input can be used to disable the device so the buses are effectively isolated.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or
pulldown resistors with the bus-hold circuitry is not recommended. The bus-hold circuitry is part of the input
circuit and is not disabled by OE or DIR.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1995–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
On products compliant to MIL-PRF-38535, all parameters are
Instruments standard warranty. Production processing does not
tested unless otherwise noted. On all other products, production
necessarily include testing of all parameters.
processing does not necessarily include testing of all parameters.


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