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AD9971 Arkusz danych(PDF) 1 Page - Analog Devices

Numer części AD9971
Szczegółowy opis  12-Bit CCD Signal Processor with Precision Timing
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12-Bit CCD Signal Processor
with Precision Timing
AD9971
Rev. SpA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006–2007 Analog Devices, Inc. All rights reserved.
FEATURES
1.8 V analog and digital core supply voltage
Serial data link with reduced range LVDS outputs
Correlated double sampler (CDS) with −3 dB, 0 dB, +3 dB,
and +6 dB gain
6 dB to 42 dB, 10-bit variable gain amplifier (VGA)
12-bit, 50 MHz ADC
Black level clamp with variable level control
Complete on-chip timing generator
Precision Timing core with 310 ps resolution @ 50 MHz
On-chip, 3 V horizontal and RG drivers
6 mm × 6 mm, 40-lead LFCSP_VQ
APPLICATIONS
Digital video camcorders
Professional/high end digital cameras
Broadcast cameras
Industrial high speed cameras
High speed data acquisition systems
GENERAL DESCRIPTION
The AD9971 is a highly integrated CCD signal processor for
high speed digital video camera applications. Specified at pixel
rates of up to 50 MHz, the AD9971 consists of a complete analog
front end with analog-to-digital conversion combined with a
programmable timing driver. The Precision Timing™ core allows
adjustment of high speed clocks with 310 ps resolution at
50 MHz operation. The AD9971 also contains a reduced range
LVDS interface for the data outputs.
The analog front end includes black level clamping, CDS, VGA,
and a 50 MSPS, 12-bit ADC. The timing driver provides the high
speed CCD clock drivers for RG, HL, and H1 to H4. Operation
is programmed using a 3-wire serial interface.
Packaged in a space-saving 6 mm × 6 mm, 40-lead LFCSP_VQ,
the AD9971 is specified over an operating temperature range of
−25°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
AD9971
CDS
VGA
CLAMP
CLI
VREF
6dB TO 42dB
4
RG
3V INPUT
1.8V OUTPUT
H1 TO H4
REFT REFB
INTERNAL CLOCKS
HD
VD
SL
SCK
SDATA
DOUT0P
DOUT1P
HL
DOUT0N
DOUT1N
TCLKP
TCLKN
–3, 0, +3, +6dB
GPO1
GPO2
CCDINP
CCDINM
REDUCED
RANGE
LVDS OUTPUT
PRECISION
TIMING
GENERATOR
HORIZONTAL
DRIVERS
12-BIT
ADC
INTERNAL
REGISTERS
SYNC
GENERATOR
LDO
REG
IOVDD
LDOOUT
Figure 1.
For more information about the AD9971, contact
Analog Devices, Inc. via email at: afe.ccd@analog.com.


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