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ADS6223IRGZR Arkusz danych(PDF) 1 Page - Texas Instruments |
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ADS6223IRGZR Arkusz danych(HTML) 1 Page - Texas Instruments |
1 / 75 page 1 FEATURES APPLICATIONS DESCRIPTION ADS6225 ,, ADS6224 ADS6223, ADS6222 SLAS543A – MAY 2007 – REVISED SEPTEMBER 2007 www.ti.com DUAL CHANNEL, 12-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS INTERFACE • Pin Compatible 14-Bit Family (ADS624X - SLAS542) • Maximum Sample Rate: 125 MSPS • Feature Compatible Quad Channel Family • 12-Bit Resolution with No Missing Codes (ADS644X - SLAS531 and ADS642X - SLAS532) • Simultaneous Sample and Hold • 3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SFDR/SNR • Base-Station IF Receivers Trade-Off • Diversity Receivers • Serialized LVDS Outputs with Programmable • Medical Imaging Internal Termination Option • Test Equipment • Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Amplitude Down to 400 mVpp Table 1. ADS62XX Dual Channel Family • Internal Reference with External Reference 125 MSPS 105 MSPS 80 MSPS 65 MSPS Support ADS624X ADS6245 ADS6244 ADS6243 ADS6242 • No External Decoupling Required for 14 Bit References ADS622X ADS6225 ADS6224 ADS6223 ADS6222 12 Bit • 3.3-V Analog and Digital Supply • 48 QFN Package (7 mm × 7 mm) Table 2. Performance Summary ADS6225 ADS6224 ADS6223 ADS6222 Fin = 10MHz (0 dB gain) 90 91 91 93 SFDR, dBc Fin = 170MHz (3.5 dB gain) 79 81 82 83 Fin = 10MHz (0 dB gain) 70.7 70.8 71.3 71.3 SINAD, dBFS Fin = 170MHz (3.5 dB gain) 67.4 68.1 68.2 68.7 Power per channel, mW 500 405 350 315 ADS6225/ADS6224/ADS6223/ADS6222 (ADS622X) is a family of high performance 12-bit 125/105/80/65 MSPS dual channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in a compact 48-pin QFN package (7 mm × 7 mm) that allows for high system integration density. The device includes 3.5 dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1 dB steps up to 6 dB. The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1 Gbps easing receiver design. The ADS622X also includes the traditional 1-wire interface that can be used at lower sampling frequencies. An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the ADC data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs. The LVDS output buffers have features such as programmable LVDS currents, current doubling modes and internal termination options. These can be used to widen eye-openings and improve signal integrity, easing capture by the receiver. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2007, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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