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ADS62P43IRGCR Arkusz danych(PDF) 9 Page - Texas Instruments |
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ADS62P43IRGCR Arkusz danych(HTML) 9 Page - Texas Instruments |
9 / 67 page ADS62P45, ADS62P44 ADS62P43, ADS62P42 REV1P0 SEP 2007 9 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. www.ti.com www.ti.com ELECTRICAL CHARACTERISTICS Typical values at 25C, min & max values are across the full temperature range TMIN = -40C to TMAX = 85C, AVDD = 3.3V, DRVDD = 3.3V, 50% clock duty cycle, -1dBFS differential analog input, internal reference, applies to CMOS & LVDS interfaces, unless otherwise noted. ADS62P45 125 MSPS ADS62P44 105 MSPS ADS62P43 80 MSPS ADS62P42 65 MSPS PARAMETERS MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNIT Fin= 10MHz 73.8 73.8 73.9 74 Fin = 50MHz TBD 73.2 73.2 TBD 73.6 73.7 Fin = 70MHz 73 TBD 73 73.4 TBD 73.5 0 dB gain 70.6 70.7 71.5 71.5 Fin = 170MHz 3.5 dB gain 70.1 70.2 70.6 70.6 0 dB gain 68.7 68.7 69.7 69.9 SINAD Signal to noise & distortion ratio, CMOS Fin = 230MHz 3.5 dB gain 68.4 68.5 69.5 69.6 dBFS Fin= 10MHz 74 74 74.1 74.1 Fin = 50MHz TBD 73.4 73.4 TBD 73.8 73.8 Fin = 70MHz 73.2 TBD 73.4 73.6 TBD 73.6 0 dB gain 70.8 70.8 71.7 71.6 Fin = 170MHz 3.5 dB gain 70.5 70.5 70.8 70.7 0 dB gain 68.9 68.9 68.1 68 SINAD Signal to noise & distortion ratio, LVDS Fin = 230MHz 3.5 dB gain 68.6 68.7 69.7 69.7 dBFS ENOB, Effective number of bits Fin = 50 MHz TBD 11.8 11.8 TBD 11.9 12 LSB |
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