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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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FM31278 Arkusz danych(PDF) 7 Page - Ramtron International Corporation |
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FM31278 Arkusz danych(HTML) 7 Page - Ramtron International Corporation |
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7 / 25 page  FM31278/276/274/272 - 5V I2C Companion Rev. 2.0 Dec. 2007 Page 7 of 25 to be loaded into the timekeeper core. W is used for writing new time values. Users should be certain not to load invalid values, such as FFh, to the timekeeping registers. Updates to the timekeeping core occur continuously except when locked. Backup Power The real-time clock/calendar is intended to be permanently powered. When the primary system power fails, the voltage on the VDD pin will drop. When VDD is less 2.5V the RTC (and event counters) will switch to the backup power supply on VBAK. The clock operates at extremely low current in order to maximize battery or capacitor life. However, one of the advantages of combining a clock function with the F-RAM memory is that data is not lost regardless of the backup power source. A battery may be inserted into a system board without any concern for excessive current draw on the FM3127x’s VBAK pin. Trickle Charger To facilitate capacitor backup, the VBAK pin can optionally provide a trickle charge current. When the VBC bit, register 0Bh bit 2, is set to ‘1’, the VBAK pin will source approximately 80 µA until VBAK reaches 3.75V. In 5V systems, this charges the capacitor to VDD without an external diode and resistor charger and also prevents the user from exceeding the VBAK maximum voltage specification. There is a Fast Charge mode which is enabled by the FC bit (register 0Bh, bit 5). In this mode the trickle charger current is set to approximately 1 mA, allowing a large backup capacitor to charge more quickly. In the case where no backup source is used, the VBAK pin should be tied to VSS. VBAK should not be tied to 5V since the VBAK (max) specification will be exceeded. Be sure to turn off the trickle charger (VBC=0), otherwise charger current will be shunted to ground from VDD. ! ! ! ! Note: systems using lithium batteries should clear the VBC bit to 0 to prevent battery charging. The VBAK circuitry includes an internal 1 K Ω series resistor as a safety element. Figure 7. Real-Time Clock Core Block Diagram Calibration When the CAL bit in a register 00h is set to 1, the clock enters calibration mode. In calibration mode, the CAL/PFO output pin is dedicated to the calibration function and the power fail output is temporarily unavailable. Calibration operates by applying a digital correction to the counter based on the frequency error. In this mode, the CAL/PFO pin is driven with a 512 Hz (nominal) square wave. Any measured deviation from 512 Hz translates into a timekeeping error. The user converts the measured error in ppm and writes the appropriate correction value to the calibration register. The correction factors are listed in the table below. Positive ppm errors require a negative adjustment that removes pulses. Negative ppm errors require a positive correction that adds pulses. Positive ppm adjustments have the CALS (sign) bit set to 1, where as negative ppm adjustments have CALS = 0. After calibration, the clock will have a maximum error of ± 2.17 ppm or ± 0.09 minutes per month at the calibrated temperature. 32.768 kHz crystal Oscillator Clock Divider Update Logic 512 Hz W R Seconds 7 bits Minutes 7 bits Hours 6 bits Date 6 bits Months 5 bits Years 8 bits CF Days 3 bits User Interface Registers 1 Hz /OSCEN |
Podobny numer części - FM31278 |
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Podobny opis - FM31278 |
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