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TDC1016J7CX Arkusz danych(PDF) 6 Page - Fairchild Semiconductor |
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TDC1016J7CX Arkusz danych(HTML) 6 Page - Fairchild Semiconductor |
6 / 12 page TDC1016 PRODUCT SPECIFICATION 6 AC Electrical Characteristics Timing Diagram Figure 1. Timing Diagram System Performance Characteristics Note: 1. In excess of theoretical DP and DG due to quantizing error. Symbol Parameter Test Conditions Temperature Range Unit Standard Extended Min. Max. Min. Max. FC Maximum Data Rate TTL Mode Full-Scale Output Step 20 20 MSPS ECL Mode Full-Scale Output Step 17.8 17.8 MSPS tDS Data Turn on Delay RL = 75 Ohms 30 30 ns tSET Settling Time TDC1016-8 to 0.2% 30 30 ns TDC1016-9 to 0.1% 35 35 ns TDC1016-10 to .05% 40 40 ns tRV Output 10% to 90% Risetime VEE = Nom., RL = 75 W, Full-Scale Step 5.5 5.5 ns Parameter Test Conditions Temperature Range Unit Standard Extended Min. Max. Min. Max. RES Resolution All TDC1016 Devices 10 10 Bits ELI, ELD Linearity Error Integral and Differential, Independent Based TDC1016-8 0.2 0.2 % FS TDC1016-9 0.1 0.1 % FS TDC1016-10 0.075 % FS VOFS Full-Scale Output Voltage VEE = Nom, RL ³ 10kW, VREF = -1.000V -0.95 -1.05 -0.95 -1.05 V VOZS Zero-Scale Output Voltage VEE = Nom, RL ³ 10 kW, VREF = -1.000V ±15 ±15 mV DP Differential Phase NTSC 4x Subcarrier1 1.0 1.0 Degrees DG Differential Gain NTSC 4x subcarrier1 1.5 1.5 % GE Glitch Energy (Area) RL = 50 W, Midscale 125 125 pV-sec GV Glitch Voltage RL = 50 W, Midscale 35 35 mV DATA CONTROLS CLOCK 1CLOCK OUTPUT NOTE: 1. Differential ECL mode only tS tH tPWL tPWH tDS tSET ±1/2 LSB ±1/2 LSB 65-1016-06 |
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