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SL23EP04SI-2T Arkusz danych(PDF) 3 Page - SpectraLinear Inc |
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SL23EP04SI-2T Arkusz danych(HTML) 3 Page - SpectraLinear Inc |
3 / 14 page Rev 1.1, May 25, 2007 Page 3 of 14 SL23EP04 General Description The SL23EP04 is a low skew, low jitter Zero Delay Buffer with very low operating current. The product includes an on-chip high performance PLL that locks into the input reference clock and produces four (4) output clock drivers tracking the input reference clock for systems requiring clock distribution. in addition to FBK pin used for internal PLL feedback, there are two (2) banks with two (2) outputs in each bank, bringing the number of total available output clocks to four (4). Input and output Frequency Range The input and output frequency is the same (1x) for SL23EP04-1 and -1H versions. For SL23EP04-2 and - 2H versions, the output frequency is 1/2x, 1x or 2x of the CLKIN as given in the “Available SL23EP04 Configurations” Table 1. But, the frequency range depends on VDD, drive levels and CL (Load Capacitance) as given in the electrical specifications tables. When the input clock frequency is DC (from GND to VDD), this input state is detected by an input level detection circuitry and all four (4) clock outputs are forced to Hi-Z. The PLL is shutdown to save power. In this shutdown state, the product draws less than 12 A (8 A –typ) supply current. SpreadThru™ Feature If a Spread Spectrum Clock (SSC) were to be used as an input clock, the SL23EP04 is designed to pass the modulated Spread Spectrum Clock (SSC) signal from its reference CLKIN input to the output clocks. The same spread spectrum characteristics at the input are passed through the PLL and drivers without any degradation in spread percent (%), spread profile and modulation frequency. High and Low-Drive Product Options All SL23EP04 products are offered with the high drive “-1H” and “-2H” as well as the standard drive “-1” and “-2” options. These drive options enable the user to control load levels, frequency range and EMI levels. Refer to the electrical tables for the details of the drive levels. Skew and Zero Delay All outputs should drive the similar load to achieve output- to-output skew and input-to-output delay specifications as given in the switching electrical tables. However, the delay between input and outputs can be adjusted by changing the load at FBK pin relative to the banks A and B clocks since FBK pin is the feedback to the internal PLL. In addition, the input reference clock rise and fall time should be similar to the output rise and fall time to obtain the best skew results. Power Supply Range (VDD) The SL23EP04 is designed to operate from 3.3V (3.63V- max) to 2.5V (2.25V-min) VDD power supply range. An internal on-chip voltage regulator is used to provide to PLL constant power supply of 1.8V internally. This leads to a consistent and stable PLL electrical performance in terms of skew, jitter and power dissipation. The SL23EP04 I/O is powered by using VDD. Contact SLI for 1.8V power supply ZDB called SL23EPL04. Device Feedback From Bank-A Frequency Bank-B Frequency SL23EP04-1 and 1H Bank-A or Bank-B Reference Reference SL23EP04-2 and -2H Bank-A Reference Reference / 2 SL23EP04-2 and -2H Bank-B 2 x Reference Reference Table 1. Available SL23EP04 Configurations |
Podobny numer części - SL23EP04SI-2T |
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Podobny opis - SL23EP04SI-2T |
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