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SL2304NZZC-1Z Arkusz danych(PDF) 7 Page - SpectraLinear Inc |
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SL2304NZZC-1Z Arkusz danych(HTML) 7 Page - SpectraLinear Inc |
7 / 9 page Rev 1.3, May 16, 2007 Page 7 of 9 SL2304NZ Switching Electrical Characteristics (I-Grade and VDD=3.3V – Cont.) Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85°C Output Fall Time tf CL=25pF, measured at 0.8V to 2.0V – – 1.6 ns CLKIN=66MHz, CL=15pF 5 – – ns CLKIN High or Low Time tHL CLKIN=140MHz, CL=15pF 2 – – ns Output to Output Skew SKW1 Measured at VDD/2 and Outputs are equally loaded – 50 100 ps Part to Part Skew SKW2 Measured at VDD/2 and Outputs are equally loaded – 90 200 ps Propagation Delay Time PDT Measured at VDD/2 from CLKIN to Output Clock rising edge and Outputs are equally loaded – 3.2 4.0 ns Cycle-to-Cycle Jitter CCJ1 CLKIN=66MHz and CL=0 (No Load) – 70 140 ps Cycle-to-Cycle Jitter CCJ2 CLKIN=133MHz and CL=0 (No Load) – 50 100 ps External Components & Design Considerations Typical Application Schematic Comments and Recommendations Decoupling Capacitor: A decoupling capacitor of 0.1 F must be used between VDD and VSS pins. Place the capacitor on the component side of the PCB as close to the VDD pin as possible. The PCB trace to the VDD pin and to the GND via should be kept as short as possible. Do not use vias between the decoupling capacitor and the VDD pin. Series Termination Resistor: A series termination resistor is recommended if the distance between the output clocks and the load is over 1 ½ inch. Place the series termination resistors as close to the clock outputs as possible. |
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