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ADCMP564 Arkusz danych(PDF) 6 Page - Analog Devices |
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ADCMP564 Arkusz danych(HTML) 6 Page - Analog Devices |
6 / 16 page ADCMP563/ADCMP564 Rev. B | Page 6 of 16 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ADCMP563 BRQ TOP VIEW (Not to Scale) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 –INA +INA QA QA GND VEE LEA LEA –INB +INB QB QB GND VCC LEB LEB Figure 5. ADCMP563 16-Lead QSOP Pin Configuration ADCMP564 BRQ TOP VIEW (Not to Scale) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 –INA QA QA GND VEE LEA LEA GND +INA HYSA –INB QB QB GND VCC LEB LEB GND +INB HYSB Figure 6. ADCMP564 20-Lead QSOP Pin Configuration ADCMP563 BCP TOP VIEW (Not to Scale) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GND –INA +INA +INB –INB QA QA QB QB LEA LEA VCC VEE GND LEB LEB PIN1 Figure 7. ADCMP563 16-Lead LFCSP Pin Configuration Table 3. Pin Function Descriptions Pin No. ADCMP563 16-Lead QSOP ADCMP563 16-Lead LFCSP ADCMP564 20-Lead QSOP Mnemonic Function 1 GND Analog Ground. 1 15 2 QA One of Two Complementary Outputs for Channel A. QA is logic high if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in compare mode). See the description of the LEA pin for more information. 2 16 3 QA One of Two Complementary Outputs for Channel A. QA is logic low if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in compare mode). See the description of the LEA pin for more information. 3 1 4 GND Analog Ground. 4 2 5 LEA One of Two Complementary Inputs for Channel A Latch Enable. In compare mode (logic high), the output tracks change at the input of the comparator. In latch mode (logic low), the output reflects the input state just prior to the comparator being placed in the latch mode. LEA must be driven in conjunction with LEA. If left unconnected, the comparator defaults to compare mode. 5 3 6 LEA One of Two Complementary Inputs for Channel A Latch Enable. In compare mode (logic low), the output tracks change at the input of the comparator. In latch mode (logic high), the output reflects the input state just prior to the comparator being placed in the latch mode. LEA must be driven in conjunction with LEA. If left unconnected, the comparator defaults to compare mode. 6 4 7 VEE Negative Supply Terminal. 7 5 8 −INA Inverting Analog Input of the Differential Input Stage for Channel A. The Inverting A input must be driven in conjunction with the Noninverting A input. 8 6 9 +INA Noninverting Analog Input of the Differential Input Stage for Channel A. The Noninverting A input must be driven in conjunction with the Inverting A input. 10 HYSA Programmable Hysteresis Input. 11 HYSB Programmable Hysteresis Input. 9 7 12 +INB Noninverting Analog Input of the Differential Input Stage for Channel B. The Noninverting B input must be driven in conjunction with the Inverting B input. 10 8 13 −INB Inverting Analog Input of the Differential Input Stage for Channel B. The Inverting B input must be driven in conjunction with the Noninverting B input. 11 9 14 VCC Positive Supply Terminal. |
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