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ADC12130CIWM Arkusz danych(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Numer części ADC12130CIWM
Szczegółowy opis  Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold
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Producent  NSC [National Semiconductor (TI)]
Strona internetowa  http://www.national.com
Logo NSC - National Semiconductor (TI)

ADC12130CIWM Arkusz danych(HTML) 3 Page - National Semiconductor (TI)

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Connection Diagrams (Continued)
28-Pin Dual-In-Line, SSOP and
Wide Body SO Packages
01207903
Top View
Ordering Information
Industrial Temperature Range
−40˚C
≤ T
A
≤ +85˚C
NS Package Number
ADC12130CIN
N16E, Dual-In-Line
ADC12130CIWM
M16B, Wide Body SO
ADC12130CIWMX
M16B, Wide Body SO - Tape & Reel
ADC12132CIMSA *
MSA20, SSOP
ADC12132CIMSAX *
MSA20, SSOP - Tape & Reel
ADC12138CIN
N28B, Dual-In-Line
ADC12138CIWM
M28B
ADC12138CIWMX
M28B - Tape & Reel
ADC12138CIMSA
MSA28, SSOP
ADC12138CIMSA
MSA28, SSOP - Tape & Reel
* The ADC12132 is obsolete and shown in this document for reference only.
Pin Descriptions
CCLK
The clock applied to this input controls the suc-
cessive approximation conversion time interval
and the acquisition time. The rise and fall times
of the clock edges should not exceed 1 µs.
SCLK
This is the serial data clock input. The clock
applied to this input controls the rate at which
the serial data exchange occurs. The rising
edge loads the information at the DI pin into the
multiplexer address and mode select shift reg-
ister. This address controls which channel of
the analog input multiplexer (MUX) is selected
and the mode of operation for the A/D. With CS
low, the falling edge of SCLK shifts the data
resulting from the previous ADC conversion out
on DO, with the exception of the first bit of data.
When CS is low continuously, the first bit of the
data is clocked out on the rising edge of EOC
(end of conversion). When CS is toggled, the
falling edge of CS always clocks out the first bit
of data. CS should be brought low when SCLK
is low. The rise and fall times of the clock edges
should not exceed 1 µs.
www.national.com
3


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