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CS80C286-20 Arkusz danych(PDF) 7 Page - Intersil Corporation |
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CS80C286-20 Arkusz danych(HTML) 7 Page - Intersil Corporation |
7 / 60 page 7 The 80C286 can be single-stepped using only the CPU clock. This state can be maintained as long as necessary. Single step clock information allows simple interface circuitry to provide critical information for system debug. Static design also allows very low frequency operation (down to DC). In a power critical situation, this can provide low power operation since 80C286 power dissipation is directly related to operating frequency. As the system fre- quency is reduced, so is the operating power until, ulti- mately, with the clock stopped in phase two of the processor clock cycle, the 80C286 power requirement is the standby current (5mA maximum). 80C286 Base Architecture The 80C86, 80C88, and 80C286 CPU family all contain the same basic set of registers, instructions, and addressing modes. The 80C286 processor is upwardly compatible with the 80C86 and 80C88 CPU's. Register Set The 80C286 base architecture has fifteen registers as shown in Figure 1. These registers are grouped into the fol- lowing four categories. GENERAL REGISTERS: Eight 16-bit general purpose regis- ters used to contain arithmetic and logical operands. Four of these (AX, BX, CX and DX) can be used either in their entirety as 16-bit words or split into pairs of separate 8-bit registers. SEGMENT REGISTERS: Four 16-bit special purpose regis- ters select, at any given time, the segments of memory that are immediately addressable for code, stack and data. (For usage, refer to Memory Organization.) BASE AND INDEX REGISTERS: Four of the general pur- pose registers may also be used to determine offset addresses of operands in memory. These registers may contain base addresses or indexes to particular locations within a segment. The addressing mode determines the spe- cific registers used for operand address calculations. STATUS AND CONTROL REGISTERS: Three 16-bit spe- cial purpose registers record or control certain aspects of the 80C286 processor state. These include the Flags register and Machine Status Word register shown in Figure 2, and the Instruction Pointer, which contains the offset address of the next sequential instruction to be executed. Flags Word Description The Flags word (Flags) records specific characteristics of the result of logical and arithmetic instructions (bits 0, 2, 4, 6, 7 and 11) and controls the operation of the 80C286 within a given operating mode (bits 8 and 9). Flags is a 16-bit regis- ter. The function of the flag bits is given in Table 1. AH AL DL CL BL DH CH BH AX DX CX BX BP SI DI SP BYTE ADDRESSABLE (8-BIT REGISTER NAMES SHOWN) MULTIPLY/DIVIDE I/O INSTRUCTIONS LOOP/SHIFT/REPEAT BASE REGISTERS COUNT INDEX REGISTERS STACK POINTER 15 0 0 7 0 7 SPECIAL REGISTER FUNCTIONS 16-BIT REGISTER NAME GENERAL REGISTERS CS DS SS ES 0 15 CODE SEGMENT SEGMENT REGISTERS SELECTOR DATA SEGMENT SELECTOR STACK SEGMENT SELECTOR EXTRA SEGMENT SELECTOR F 0 15 FLAGS INSTRUCTION MACHINE POINTER STATUS WORD IP MSW STATUS AND CONTROL REGISTERS FIGURE 1. REGISTER SET 80C286 |
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