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ADSP-BF538F Arkusz danych(PDF) 11 Page - Analog Devices |
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ADSP-BF538F Arkusz danych(HTML) 11 Page - Analog Devices |
11 / 56 page ADSP-BF538/ADSP-BF538F Rev. 0 | Page 11 of 56 | May 2007 processor. For SPI0, seven SPI chip select output pins (SPI0SEL7–1) let the processor select other SPI devices. SPI1 and SPI2 each have a single SPI chip select output pin (SPI1SEL1 and SPI2SEL1) for SPI point-to-point communica- tion. Each of the SPI select pins are reconfigured GPIO pins. Using these pins, the SPI ports provide a full-duplex, synchro- nous serial interface, which supports both master/slave modes and multimaster environments. The SPI ports’ baud rate and clock phase/polarities are pro- grammable, and it has an integrated DMA controller, configurable to support transmit or receive data streams. Each SPI’s DMA controller can only service unidirectional accesses at any given time. The SPI port’s clock rate is calculated as: Where the 16-bit SPIx_BAUD register contains a value of 2 to 65,535. During transfers, the SPI port simultaneously transmits and receives by serially shifting data in and out on its two serial data lines. The serial clock line synchronizes the shifting and sam- pling of data on the two serial data lines. 2-WIRE INTERFACE The ADSP-BF538/ADSP-BF538F processors have two 2-wire interface (TWI) modules that are compatible with the Philips Inter-IC bus standard. The TWI modules offer the capabilities of simultaneous master and slave operation, support for 7-bit addressing and multimedia data arbitration. The TWI also includes master clock synchronization and support for clock low extension. The TWI interface uses two pins for transferring clock (SCLx) and data (SDAx) and supports the protocol at speeds up to 400 kbps. The TWI interface pins are compatible with 5 V logic levels. UART PORTs The ADSP-BF538/ADSP-BF538F processors incorporate three full-duplex Universal Asynchronous Receiver/Transmitter (UART) ports, which are fully compatible with PC standard UARTs. The UART ports provide a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMA sup- ported, asynchronous transfers of serial data. The UART ports include support for 5 data bits to 8 data bits, 1 stop bit or 2 stop bits, and none, even, or odd parity. The UART ports support two modes of operation: • PIO (programmed I/O) – The processor sends or receives data by writing or reading I/O mapped UART registers. The data is double buffered on both transmit and receive. • DMA (direct memory access) – The DMA controller trans- fers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. Each UART has two dedicated DMA channels, one for transmit and one for receive. These DMA channels have lower default priority than most DMA channels because of their relatively low service rates. Each UART port’s baud rate, serial data format, error code gen- eration and status, and interrupts are programmable: • Supporting bit rates ranging from (fSCLK/ 1,048,576) to (fSCLK/16) bits per second. • Supporting data formats from 7 to12 bits per frame. • Both transmit and receive operations can be configured to generate maskable interrupts to the processor. Each UART port’s clock rate is calculated as: Where the 16-bit UART_Divisor comes from the UARTx_DLH register (most significant 8 bits) and UARTx_DLL register (least significant 8 bits). In conjunction with the general-purpose timer functions, auto- baud detection is supported on UART0. The capabilities of the UARTs are further extended with sup- port for the Infrared Data Association (IrDA) Serial Infrared Physical Layer Link Specification (SIR) protocol. GENERAL-PURPOSE PORTS The ADSP-BF538/ADSP-BF538F processors have up to 54 gen- eral-purpose I/O pins that are multiplexed with other peripherals. They are arranged into ports C, D, E, and F as shown in Table 4. The general-purpose I/O pins may be individually controlled by manipulation of the control and status registers. These pins may be polled to determine their status. • GPIO direction control register – Specifies the direction of each individual GPIO pin as input or output. • GPIO control and status registers – The processor employs a “write one to modify” mechanism that allows any combi- nation of individual GPIO to be modified in a single instruction, without affecting the level of any other GPIO. Four control registers and a data register are provided for each GPIO port. One register is written in order to set GPIO values, one register is written in order to clear GPIO values, one register is written in order to toggle GPIO val- ues, and one register is written in order to specify a GPIO input or output. Reading the GPIO data allows software to determine the state of the input GPIO pins. In addition to the GPIO function described above, the 16 port F pins can be individually configured to generate interrupts. • GPIO Pin interrupt mask registers – The two GPIO pin interrupt mask registers allow each individual PFx pin to function as an interrupt to the processor. Similar to the two GPIO control registers that are used to set and clear indi- vidual GPIO pin values, one GPIO pin interrupt mask register sets bits to enable interrupt function, and the other GPIO pin interrupt mask register clears bits to disable SPI Clock Rate fSCLK 2SPIx_BAUD × --------------------------------------- = UART Clock Rate fSCLK 16 UART_Divisor × ----------------------------------------------- = |
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