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ADSP-BF538BBCZ-4F4 Arkusz danych(PDF) 1 Page - Analog Devices |
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ADSP-BF538BBCZ-4F4 Arkusz danych(HTML) 1 Page - Analog Devices |
1 / 56 page Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc. Blackfin® Embedded Processor ADSP-BF538/ADSP-BF538F Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. FEATURES Up to 533 MHz high performance Blackfin processor Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter RISC-like register and instruction model for ease of program- ming and compiler friendly support Advanced debug, trace, and performance monitoring 0.85 V to 1.25 V core VDD with on-chip voltage regulation 2.5 V to 3.3 V I/O VDD Up to 3.3 V tolerant I/O with specific 5 V tolerant pins 316-ball Pb-free mini-BGA package MEMORY 148K bytes of on-chip memory: 16K bytes of instruction SRAM/cache 64K bytes of instruction SRAM 32K bytes of data SRAM 32K bytes of data SRAM/cache 4K bytes of scratchpad SRAM 512K 16-bit or 256K 16-bit of flash memory (ADSP-BF538F only) Memory management unit providing memory protection External memory controller with glueless support for SDRAM, SRAM, flash, and ROM Flexible memory booting options from SPI® and external memory PERIPHERALS Parallel peripheral interface (PPI) supporting ITU-R 656 video data formats Four dual-channel, full-duplex synchronous serial ports, supporting 16 stereo I 2S® channels Two DMA controllers supporting 26 peripheral DMAs Four memory-to-memory DMAs Controller area network (CAN) 2.0B controller Three SPI-compatible ports Three 32-bit timer/counters with PWM support Three UARTs with support for IrDA ® Two TWI controllers compatible with I2C® industry standard Up to 54 general-purpose I/O pins (GPIO) Real time clock, watchdog timer, and 32-bit core timer On-chip PLL capable of 0.5 to 64 frequency multiplication Debug/JTAG interface Figure 1. Functional Block Diagram UAR T0 SP O R T 0-1 WA T C H D O G TIM E R RTC SP I0 TIM ER 0-2 PP I SPI1-2 SPO R T2-3 UART1-2 GPIO PO RT F GP IO PO R T D GP IO PO R T C GP IO PO R T E E X TE RNA L P O R T FL ASH , S DRAM CO NT RO L BOO T ROM JTAG T EST AND EM ULATIO N V O LT AG E R EG ULAT O R DM A CO NT RO L LER 0 L1 IN ST RU CTIO N MEM O R Y L1 DAT A MEMO R Y B IN TE RRUP T CO NT RO LL ER PE RIPHERA L ACCES S BUS D M A C ORE BUS 0 DM A EXTER NAL BUS 1 TW I0-1 CAN 2.0B GPIO 512kB O R 1M B FLA SH M E M O R Y (A D SP-B F538F O N LY ) DM A CO NTRO L LE R 1 DM A C O R E BUS 1 DMA EXTER NAL BUS 0 16 |
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