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M27V402-200B1TR Arkusz danych(PDF) 2 Page - STMicroelectronics

Numer części M27V402-200B1TR
Szczegółowy opis  4 Mbit (256Kb x 16) Low Voltage UV EPROM and OTP EPROM
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Producent  STMICROELECTRONICS [STMicroelectronics]
Strona internetowa  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

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M27V402
2/15
Figure 2B. LCC Pin Connections
Warning: NC = Not Connected.
AI01820
A11
A7
23
Q6
Q5
Q4
Q12
Q8
VSS
NC
Q11
Q10
12
A9
1
VSS
A12
A5
44
M27V402
A13
NC
A6
34
Q9
A10
A8
Q7
Figure 2A. DIP Pin Connections
Q6
Q5
Q4
Q11
Q8
VSS
Q7
Q10
Q9
A12
A8
A11
A10
A6
A13
A9
VSS
A7
A2
Q1
Q0
A0
G
A1
A5
A16
A17
E
Q12
VPP
VCC
Q15
AI01862
M27V402
8
1
2
3
4
5
6
7
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Q3
Q2
Q14
Q13
A4
A3
40
39
38
37
36
35
34
33
A14
A15
For applications where the content is programmed
only one time and erasure is not required, the
M27V256 is offered in PDIP40, PLCC44 and
TSOP40 (10 x 20 mm) packages.
DEVICE OPERATION
The operating modes of the M27V402 are listed in
the Operating Modes table. A single power supply
is required in the read mode. All inputs are TTL
levels except for VPP and 12V on A9 for Electronic
Signature.
Read Mode
The M27V402 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins,
independent of device selection. Assuming that
the addresses are stable, the address access time
(tAVQV) is equal to the delay from E to output
(tELQV). Data is available at the output after a delay
of tGLQV from the falling edge of G, assuming that
E has been low and the addresses have been
stable for at least tAVQV-tGLQV.
Figure 2C. TSOP Pin Connections
DQ6
DQ3
DQ2
DQ13
DQ8
DQ7
DQ10
DQ9
A14
A8
A11
A10
A4
A15
A9
G
A7
A2
DQ1
DQ0
A0
A1
A3
A16
A17
E
DQ14
VPP
VCC
DQ15
AI01821
M27V402
(Normal)
10
1
11
20
21
30
31
40
VSS
A13
A12
A6
A5
DQ11
DQ12
DQ5
DQ4
VSS


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