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ST7PLITEU09M6 Arkusz danych(PDF) 7 Page - STMicroelectronics |
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ST7PLITEU09M6 Arkusz danych(HTML) 7 Page - STMicroelectronics |
7 / 115 page ST7LITEU05 ST7LITEU09 7/115 PIN DESCRIPTION (Cont’d) Legend / Abbreviations for Table 2: Type: I = input, O = output, S = supply In/Output level: CT= CMOS 0.3VDD/0.7VDD with input trigger Output level: HS = High sink (on N-buffer only) Port and control configuration: – Input:float = floating, wpu = weak pull-up, int = in- terrupt, ana = analog – Output: OD = open drain, PP = push-pull The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state. Table 2. Device Pin Description Note: 1. It is mandatory to connect all available VDD and VDDA pins to the supply voltage and all VSS and VSSA pins to ground. 2. After a reset, the multiplexed PA3/RESET pin will act as RESET. To configure this pin as output (Port A3), write 55h to MUXCR0 and AAh to MUXCR1. For further details, please refer to section 7.4 on page 30. Pin No. Pin Name Level Port / Control Main Function (after reset) Alternate Function Input Output 1VDD 1) S Main power supply 2 PA5/AIN4/ CLKIN I/O CT HS X ei4 X X X Port A5 Analog input 4 or External Clock Input 3 PA4/AIN3/MCO I/O CT HS X ei3 X X X Port A4 Analog input 3 or Main clock output 4 PA3/RESET 2) O X XX Port A3 RESET 2) 5 PA2/AIN2/LTIC I/O CT HS X ei2 X X X Port A2 Analog input 2 or Lite Timer Input Cap- ture 6 PA1/AIN1/ ICCCLK I/O CT HS X ei1 XX X Port A1 Analog input 1 or In Circuit Communica- tion Clock Caution: During normal operation this pin must be pulled-up, internally or ex- ternally (external pull-up of 10k manda- tory in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset. In the application, even if the pin is configured as output, any re- set will put it back in pull-up 7 PA0/AIN0/ATP- WM/ICCDATA I/O CT HS X ei0 X X X Port A0 Analog input 0 or Auto-Reload Timer PWM or In Circuit Communication Data 8VSS 1) S Ground 1 |
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