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ADS61B23IRHBT Arkusz danych(PDF) 8 Page - Texas Instruments |
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ADS61B23IRHBT Arkusz danych(HTML) 8 Page - Texas Instruments |
8 / 51 page www.ti.com DIGITAL CHARACTERISTICS (1) ADS61B23 SLAS582 – FEBRUARY 2008 The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1 with AVDD = 3.0 to 3.6 V. PARAMETER TEST CONDITIONS ADS61B23 MIN TYP MAX UNIT DIGITAL INPUTS High-level input voltage 2.4 V Low-level input voltage 0.8 V High-level input current 33 µA Low-level input current –33 µA Input capacitance 4 pF DIGITAL OUTPUTS – CMOS INTERFACE, DRVDD = 1.65 to 3.6 V High-level output voltage DRV V DD Low-level output voltage 0 V Output capacitance inside the device, from each output to Output capacitance 2 pF ground DIGITAL OUTPUTS – LVDS INTERFACE, DRVDD = 3.0 V to 3.6 V, IO = 3.5 mA, RL = 100 Ω (2) High-level output voltage 1375 mV Low-level output voltage 1025 mV Output differential voltage, |VOD| 225 350 mV VOS Output offset voltage, single-ended Common-mode voltage of OUTP, OUTM 1200 mV Output capacitance inside the device, from either output to Output capacitance 2 pF ground (1) All LVDS and CMOS specifications are characterized, but not tested at production. (2) IO Refers to the LVDS buffer current setting, RL is the differential load resistance between the LVDS output pair. 8 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS61B23 |
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