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M74HC109 Arkusz danych(PDF) 1 Page - STMicroelectronics |
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M74HC109 Arkusz danych(HTML) 1 Page - STMicroelectronics |
1 / 11 page M54HC109 M74HC109 December 1992 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR B1R (Plastic Package) ORDER CODES : M54HC109F1R M74HC109M1R M74HC109B1R M74HC109C1R F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) PIN CONNECTIONS (top view) NC = No Internal Connection INPUT AND OUTPUT EQUIVALENT CIRCUIT DESCRIPTION . HIGH SPEED fMAX = 63 MHz (TYP.) AT VCC =5 V . LOW POWER DISSIPATION ICC =2 µA (MAX.) AT TA =25 °C . HIGH NOISE IMMUNITY VNIH =VNIL =28 % VCC (MIN.) . OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS . SYMMETRICAL OUTPUT IMPEDANCE IOH =IOL = 4 mA (MIN.) . BALANCED PROPAGATION DELAYS tPLH =tPHL . WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V . PIN AND FUNCTION COMPATIBLE WITH 54/74LS109 The M54/74HC109 is a high speed CMOS DUAL J- K FLIP-FLOP WITH PRESET AND CLEAR fabri- cated in silicon gate C 2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. In accordance with the logic level on the J and K input is device changes state on positive going tran- sitions of the clock pulse. CLEAR and PRESET are independent of the clock and accomplished by a low logic level on the corresponding input. All inputs are equipped with protection circuits against static discharge and transient excess volt- age. 1/11 |
Podobny numer części - M74HC109 |
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Podobny opis - M74HC109 |
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