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ADSP-21266SKBCZ-2D Arkusz danych(PDF) 6 Page - Analog Devices

Numer części ADSP-21266SKBCZ-2D
Szczegółowy opis  Embedded Processor
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Rev. C
|
Page 6 of 44
|
October 2007
ADSP-21266
Fourier transforms. The two DAGs of the ADSP-21266 contain
sufficient registers to allow the creation of up to 32 circular buff-
ers (16 primary register sets, 16 secondary). The DAGs
automatically handle address pointer wraparound, reduce over-
head, increase performance, and simplify implementation.
Circular buffers can start and end at any memory location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations for concise programming. For example, the
ADSP-21266 can conditionally execute a multiply, an add, and a
subtract in both processing elements while branching and fetch-
ing up to four 32-bit values from memory—all in a single
instruction.
ADSP-21266 MEMORY AND I/O INTERFACE
FEATURES
The ADSP-21266 adds the following architectural features to
the SIMD SHARC family core:
Dual-Ported On-Chip Memory
The ADSP-21266 contains two megabits of internal SRAM and
four megabits of internal mask-programmable ROM. Each
block can be configured for different combinations of code and
data storage (see memory map, Figure 3). Each memory block is
dual-ported for single-cycle, independent accesses by the core
processor and I/O processor. The dual-ported memory, in com-
bination with three separate on-chip buses, allows two data
transfers from the core and one from the I/O processor, in a sin-
gle cycle.
The ADSP-21266 is available with a variety of multichannel
surround-sound decoders, preprogrammed in on-chip ROM
memory. Table 2 indicates the configurations of decoder algo-
rithms provided.
The ADSP-21266’s SRAM can be configured as a maximum of
64K words of 32-bit data, 128K words of 16-bit data, 42K words
of 48-bit instructions (or 40-bit data), or combinations of differ-
ent word sizes up to two megabits. All of the memory can be
accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit float-
ing-point storage format is supported that effectively doubles
the amount of data that can be stored on-chip. Conversion
between the 32-bit floating-point and 16-bit floating-point for-
mats is performed in a single instruction. While each memory
block can store combinations of code and data, accesses are
most efficient when one block stores data using the DM bus for
transfers, and the other block stores instructions and data using
the PM bus for transfers.
Using the DM bus and PM buses, with one dedicated to each
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in
the cache.
DMA Controller
The ADSP-21266’s on-chip DMA controller allows zero-over-
head data transfers without processor intervention. The DMA
controller operates independently and invisibly to the processor
core, allowing DMA operations to occur while the core is simul-
taneously executing its program instructions. DMA transfers
can occur between the ADSP-21266’s internal memory and its
serial ports, the SPI-compatible (serial peripheral interface)
port, the IDP (input data port), parallel data acquisition port
(PDAP), or the parallel port. Twenty-two channels of DMA are
available on the ADSP-21266—one for the SPI interface, 12 via
the serial ports, eight via the input data port, and one via the
processor’s parallel port. Programs can be downloaded to the
ADSP-21266 using DMA transfers. Other DMA features
include interrupt generation upon completion of DMA trans-
fers, and DMA chaining for automatic linked DMA transfers.
Digital Audio Interface (DAI)
The digital audio interface provides the ability to connect vari-
ous peripherals to any of the SHARC DSP’s DAI pins
(DAI_P20–1).
Connections are made using the signal routing unit (SRU,
shown in the block diagram on Page 1).
The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by the DAI to be intercon-
nected under software control. This allows easy use of the DAI
associated peripherals for a much wider variety of applications
by using a larger set of algorithms than is possible with noncon-
figurable signal paths.
The DAI also includes six serial ports, two precision clock gen-
erators (PCGs), an input data port (IDP), six flag outputs and
six flag inputs, and three timers. The IDP provides an additional
input path to the ADSP-21266 core, configurable as either eight
channels of I2S or serial data, or as seven channels plus a single
20-bit wide synchronous parallel data acquisition port. Each
data channel has its own DMA channel that is independent
from the ADSP-21266’s serial ports.
For complete information on using the DAI, see the
ADSP-2126x SHARC DSP Peripherals Manual.
Serial Ports
The ADSP-21266 features six full duplex synchronous serial
ports that provide an inexpensive interface to a wide variety of
digital and mixed-signal peripheral devices such as the Analog
Devices AD183x family of audio codecs, ADCs, and DACs. The
Table 2. Multichannel Surround-Sound Decoder Algorithms
in On-Chip ROM
Algorithms
B ROM
C ROM
D ROM
PCM
Yes
Yes
Yes
AC-3
Yes
Yes
Yes
DTS 96/24
v2.2
v2.3
v2.3
AAC (LC)
Yes
Yes
Coefficients only
WMAPRO 7.1 96 KHz
No
No
Yes
MPEG2 BC 2ch
Yes
Yes
No
Noise
Yes
Yes
Yes
DPL2x/EX
DPL2
Yes
Yes
Neo:6/ES (v2.5046)
Yes
Yes
Yes


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