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DAC7565IAPW Arkusz danych(PDF) 5 Page - Texas Instruments

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Numer części DAC7565IAPW
Szczegółowy opis  12-Bit, Quad Channel, Ultra-Low Glitch, Voltage Output DIGITAL-TO-ANALOG CONVERTER with 2.5V, 2ppm/째C Internal Reference
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Producent  TI [Texas Instruments]
Strona internetowa  http://www.ti.com
Logo TI - Texas Instruments

DAC7565IAPW Arkusz danych(HTML) 5 Page - Texas Instruments

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PIN CONFIGURATIONS
DAC7565
V
A
OUT
V
B
OUT
V
H/V
OUT
REF
REF
AV
DD
LDAC
ENABLE
RSTSEL
RST
1
2
3
4
16
15
14
13
V
L
REF
GND
V
OUTC
5
6
7
V
OUTD
8
IOV
DD
D
IN
12
11
10 SCLK
SYNC
9
DAC7565
www.ti.com ............................................................................................................................................... SBAS412A – FEBRUARY 2008 – REVISED MARCH 2008
PW PACKAGE
TSSOP-16
(Top View)
PIN DESCRIPTIONS
PIN
NAME
DESCRIPTION
1
VOUTA
Analog output voltage from DAC A
2
VOUTB
Analog output voltage from DAC B
VREFH/
3
Positive reference input / reference output 2.5V if internal reference used.
VREFOUT
4
AVDD
Power-supply input, 2.7V to 5.5V
5
VREFL
Negative reference input
6
GND
Ground reference point for all circuitry on the part
7
VOUTC
Analog output voltage from DAC C
8
VOUTD
Analog output voltage from DAC D
Level-triggered control input (active low). This input is the frame synchronization signal for the input data. When SYNC
goes low, it enables the input shift register, and data are sampled on subsequent falling clock edges. The DAC output
9
SYNC
updates following the 24th clock. If SYNC is taken high before the 24th clock edge, the rising edge of SYNC acts as
an interrupt, and the write sequence is ignored by the DAC7565. Schmitt-Trigger logic input.
10
SCLK
Serial clock input. Data can be transferred at rates up to 50MHz. Schmitt-Trigger logic input.
Serial data input. Data are clocked into the 24-bit input shift register on each falling edge of the serial clock input.
11
DIN
Schmitt-Trigger logic input.
12
IOVDD
Digital input-output power supply
Asynchronous reset. Active low. If RST is low, all DAC channels reset either to zero-scale (RSTSEL = 0) or to
13
RST
mid-scale (RSTSEL = 1)
14
RSTSEL
Reset select. If RSTSEL is low, input coding is binary; if high = two's complement.
15
ENABLE
The enable pin (active low) connects the SPI interface to the serial port
16
LDAC
Load DACs; rising edge triggered, loads all DAC registers
Copyright © 2008, Texas Instruments Incorporated
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