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UC2914DWTRG4 Arkusz danych(PDF) 10 Page - Texas Instruments |
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UC2914DWTRG4 Arkusz danych(HTML) 10 Page - Texas Instruments |
10 / 24 page UC2914 UC3914 SLUS425C − DECEMBER 2003 − REVISED JULY 2004 10 www.ti.com APPLICATION INFORMATION The output voltage waveforms have assumed an R-C characteristic load and time constants vary depending upon the component values. Prior to time t0, the load is fully charged to almost VVCC and the N-channel MOSFET is supplying the current, IOUT, to the load. At t0, the current begins to ramp up due to a change in the load conditions until, at t1, the fault current level, IFAULT, has been reached to cause switch S1 to close. This results in CT being charged with the current sources I1 and IPL. During this time, VOUT remains almost equal to VVCC except for small losses from voltage drops across the sense resistor and the N-channel MOSFET. The output current reaches the programmed maximum level, IMAX, at t2. The CT voltage continues to rise since IMAX is still greater than IFAULT. The load output voltage drops because the current load requirements have become greater than the controlled maximum sourcing current. The CT voltage reaches the upper comparator threshold (Figure 2) of 2.5 V at t3, which promptly shuts off the gate drive to the N-channel MOSFET (not shown but can be inferred from the fact that no output current is provided to the load), latches in the fault and opens switch S1 disconnecting the charging currents I1 and IPL from CT. Since no output current is supplied, the load voltage decays at a rate determined by the load characteristics and the capacitance. The 3- µA current source, I2, discharges CT to the 0.5-V reset comparator threshold. This time is significantly longer than the charging time and is the basis for the duty cycle current limiting technique. When the CT voltage reaches 0.5 V at t4, the part performs a retry, allowing the N-channel MOSFET to again source current to the load and cause VOUT to rise. In this particular example, IMAX is still sourced by the N-channel MOSFET at each attempted retry and the fault timing sequence is repeated until time t7 when the load requirements change to IOUT. Since IOUT is less than the fault current level at this time, switch S1 is opened, I2 discharges CT and VOUT rises almost to the level of VCC. Figure 4 shows fault timing waveforms similar to those depicted in Figure 3 except that the latch reset (LR) function is utilized. Operation is the same as described above until t4 when the voltage on CT reaches the reset threshold. Holding LR high prevents the latch from being reset, preventing the device from performing a retry (sourcing current to the load). The UC3914 is latched off until either LR is pulled to a logic low, or the chip is forced into an under voltage lockout (UVLO) condition and back out of UVLO causing the latch to automatically perform a power on reset. Figure 4 illustrates LR being toggled low at t5, causing the part to perform a retry. Time t6 again illustrates what happens when a fault is detected. The LR pin is toggled low and back high at time t7, prior to the voltage on the CT pin hitting the reset threshold. This information tells the UC3914 to allow the part to perform a retry when the lower reset threshold is reached, which occurs at t8. Time t9 corresponds to when load conditions change to where a fault is not present as described for Figure 3. |
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