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RIVA128 Arkusz danych(PDF) 6 Page - STMicroelectronics |
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RIVA128 Arkusz danych(HTML) 6 Page - STMicroelectronics |
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6 / 77 page  128-BIT 3D MULTIMEDIA ACCELERATOR RIVA 128 6/77 2 PIN DESCRIPTIONS 2.1 ACCELERATED GRAPHICS PORT (AGP) INTERFACE 2.2 PCI 2.1 LOCAL BUS INTERFACE Signal I/O Description AGPST[2:0] I AGP status bus providing information from the arbiter to the RIVA 128 on what it may do. AGPST[2:0] only have meaning to the RIVA 128 when PCIGNT# is asserted. When PCIGNT# is de-asserted these signals have no meaning and must be ignored. 000 Indicates that previously requested low priority read or flush data is being returned to the RIVA 128. 001 Indicates that previously requested high priority read data is being returned to the RIVA 128. 010 Indicates that the RIVA 128 is to provide low priority write data for a previous enqueued write command. 011 Indicates that the RIVA 128 is to provide high priority write data for a previous enqueued write command. 100 Reserved 101 Reserved 110 Reserved 111 Indicates that the RIVA 128 has been given permission to start a bus transac- tion. The RIVA 128 may enqueue AGP requests by asserting AGPPIPE# or start a PCI transaction by asserting PCIFRAME#. AGPST[2:0] are always an output from the Core Logic (AGP chipset) and an input to the RIVA 128. AGPRBF# O Read Buffer Full indicates when the RIVA 128 is ready to accept previously requested low priority read data or not. When AGPRBF# is asserted the arbiter is not allowed to return (low priority) read data to the RIVA 128. This signal should be pulled up via a 4.7K Ω resis- tor (although it is supposed to be pulled up by the motherboard chipset). AGPPIPE# O Pipelined Read is asserted by RIVA 128 (when the current master) to indicate a full width read address is to be enqueued by the target. The RIVA 128 enqueues one request each rising clock edge while AGPPIPE# is asserted. When AGPPIPE# is de-asserted no new requests are enqueued across PCIAD[31:0]. AGPPIPE# is a sustained tri-state signal from the RIVA 128 and is an input to the target (the core logic). AGPADSTB0 ∗, AGPADSTB1 ∗ I/O These signals are currently a “no-connect” in this revision of the RIVA 128 but may be acti- vated to support AGP double-edge clocking in future pin compatible devices. It is recom- mended that these pins are connected directly to the AD_STB0 and AD_STB1 pins defined in the AGP specification. Signal I/O Description PCICLK I PCI clock. This signal provides timing for all transactions on the PCI bus, except for PCIRST# and PCIINTA#. All PCI signals are sampled on the rising edge of PCICLK and all timing parameters are defined with respect to this edge. PCIRST# I PCI reset. This signal is used to bring registers, sequencers and signals to a consistent state. When PCIRST# is asserted all output signals are tristated. PCIAD[31:0] I/O 32-bit multiplexed address and data bus. A bus transaction consists of an address phase followed by one or more data phases. |
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