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74LVCE161284DLG4 Arkusz danych(PDF) 3 Page - Texas Instruments |
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74LVCE161284DLG4 Arkusz danych(HTML) 3 Page - Texas Instruments |
3 / 16 page www.ti.com See Note A See Note A See Note B B1-B8 Y9-Y13 PERI LOGIC OUT C14-C17 HOST LOGIC IN VCC CABLE DIR HD A1-A8 A9-A13 PERI LOGIC IN A14-A17 HOST LOGIC OUT 42 48 1 19 24 30 25 NOTES: A. The PMOS transistors prevent backdriving current from the signal pins to VCC CABLE when VCC CABLE is open or at GND. The PMOS transistor is turned off when the associated driver is in the low state. B. The PMOS transistor prevents backdriving current from the signal pins to VCC CABLE when VCC CABLE is open or at GND. C. Active input detection circuit forces Y9-Y13 to the high state after power-on, until one of the A9-A13 goes high (see Figure 1). See Note C SN74LVCE161284 19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP SCES541 – JANUARY 2004 – REVISED MARCH 2005 LOGIC DIAGRAM 3 |
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