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CS5542-KL Arkusz danych(PDF) 1 Page - Cirrus Logic

Numer części CS5542-KL
Szczegółowy opis  22-Bit, Multi-Channel DS ADC Chip Set
Download  30 Pages
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Producent  CIRRUS [Cirrus Logic]
Strona internetowa  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS5542-KL Arkusz danych(HTML) 1 Page - Cirrus Logic

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Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
1
Copyright
© Cirrus Logic, Inc. 1997
(All Rights Reserved)
Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
CS5542
CS5543
22-Bit, Multi-Channel
∆Σ ADC Chip Set
Features
l Delta-Sigma Architecture:
- 5th Order Modulator
- 22-Bit Resolution
l dc Accuracy (fBW = 250Hz):
- Integral Linearity: ±0.001 % F.S.
- Differential Linearity: ±0.5 LSBs
- RMS Noise: 1.1 pARMS
l Pin Selectable Input Range:
- ±400 nA to ±2.5 µA Full Scale
l 8-Channel Digital FIR Filter
l Self-calibration of Offset and Gain
l Low Power: 50 mW /ch for 8-ch system
Description
The CS5542 / CS5543 chip set is designed to be a com-
plete current measurement data acquisition system.
The CS5542 is a 22-Bit, 2-channel, 5th-order delta sig-
ma modulator. The CS5543 is a monolithic CMOS, 8-
channel digital FIR filter designed to be used with up to
four CS5542’s forming an 8-channel system. The com-
plete system is capable of cascading up to 1024
channels.
The system supports 22-bit measurement resolution
with output conversion rates up to 1 kHz per channel.
JTAG boundary-scan capability is available to facilitate
self-test at the system level.
Potential applications for the CS5542/CS5543 system
are environmental monitoring, process control systems,
color sensing, light measurement, chemical analyzers
and photo-diode transducer applications.
ORDERING INFORMATION
CS5542-KL
0 to 70°C
28-pin PLCC
CS5543-KL
0 to 70°C
28-pin PLCC
REFGNDL
INL
ICAL
INR
REFGNDR
VA+
VA- GNDL VD+ DGND
VREF+ VREF- GNDR SEL0SEL1
CAPSIZE
PDN
MCLK
FSYNC
CAL[1:0]
MDATA[3:0]
C[2:0]
Calibra-
and
Digital
Control
Logic
5th Order
Bias
ICAL
MUX
Delta-Sigma
Modulator
Right
5th Order
Delta-Sigma
Modulator
Left
CAPSIZE
MCLK
FSYNC
PDN
C[2.0]
CAL[1:0]
TCK
TMS
TDI
TDO
VD1+GND1VD2+GND2VD3+GND3
Channel
Channel
Regulator
tion
Control/Sequencing
3
2
DMODE[2:0]
RST
CLKIN
FEGAIN
OE
DATSEL[3:0]
3
4
Test
Access
Port
MDATA
4
Serial I/O
DATAIN[3:0]
4
DATAOUT
4
[3:0]
DATACLK
FRAME
[3:0]
CS5543
CS5542
SEP ‘96
DS109PP2


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