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ADG527AKN Arkusz danych(PDF) 3 Page - Analog Devices |
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ADG527AKN Arkusz danych(HTML) 3 Page - Analog Devices |
3 / 20 page ADG526A/ADG527A Rev. C | Page 3 of 20 SPECIFICATIONS DUAL SUPPLY VDD = 10.8 V to 16.5 V, VSS = −10.8 V to −16.5 V, unless otherwise noted. Table 1. Parameter ADG526A/ADG527A ADG526A Unit Comments K Version B Version T Version 25°C −40°C to +85°C 25°C −40°C to +85°C 25°C −55°C to +125°C ANALOG SWITCH Analog Signal Range VSS VSS VSS VSS VSS VSS V min VDD VDD VDD VDD VDD VDD V max RON 280 280 280 Ω typ −10 V ≤ VS ≤ +10 V, IDS = 1 mA; see Figure 15 450 600 450 600 450 600 Ω max 300 400 300 400 Ω max VDD = +15 V (±10%), VSS = −15 V (±10%) 300 400 Ω max VDD = +15 V (±5%), VSS = −15 V (±5%) RON Drift 0.6 0.6 0.6 %/°C typ −10 V ≤ VS ≤ +10 V, IDS = 1 mA RON Match 5 5 5 % typ −10 V ≤ VS ≤ +10 V, IDS = 1 mA IS (Off), Off Input Leakage 0.02 0.02 0.02 nA typ V1 = ±10 V, V2 = 10 V; see Figure 16 1 50 1 50 1 50 nA max ID (Off), Off Output Leakage 0.04 0.04 0.04 nA typ V1 = ±10 V, V2 = 10 V; see Figure 17 ADG526A 1 200 1 200 1 200 nA max ADG527A 1 100 1 100 nA max ID (On), On Channel Leakage 0.04 0.04 0.04 nA typ V1 = ±10 V, V2 = 10 V; see Figure 18 ADG526A 1 200 1 200 1 200 nA max ADG527A 1 100 1 100 nA max IDIFF, Differential Off Output Leakage 25 25 nA max V1 = ±10 V, V2 = 10 V; see Figure 19 (ADG527A Only) DIGITAL CONTROL VINH, Input High Voltage 2.4 2.4 2.4 V min VINL, Input Low Voltage 0.8 0.8 0.8 V max IINL or IINH 1 1 1 μA max VIN = 0 to VDD CIN, Digital Input Capacitance 8 8 8 pF max DYNAMIC CHARACTERISTICS1 tTRANSITION 200 200 200 ns typ V1 = ±10 V, V2 = 10 V; see Figure 20 300 400 300 400 300 400 ns max tOPEN 50 50 50 ns typ See Figure 21 25 10 25 10 25 10 ns min tON (EN, WR) 200 200 200 ns typ See Figure 22 and Figure 23 300 400 300 400 300 400 ns max tOFF (EN, RS) 200 200 200 ns typ See Figure 22 and Figure 24 300 400 300 400 300 400 ns max tW , Write Pulse Width 100 120 100 120 100 130 ns min See Figure 13 tS, Address Enable Setup Time 100 100 100 ns min See Figure 13 tH, Address Enable Hold Time 10 10 10 ns min See Figure 13 tRS, Reset Pulse Width 100 100 100 ns min See Figure 14 |
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