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AD9220AR Arkusz danych(PDF) 11 Page - Analog Devices

Numer części AD9220AR
Szczegółowy opis  Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D Converters
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REV. E
AD9221/AD9223/AD9220
–11–
Referring to Figure 5, the differential SHA is implemented using a
switched-capacitor topology. Therefore, its input impedance
and its subsequent effects on the input drive source should be
understood to maximize the converter’s performance. The com-
bination of the pin capacitance, CPIN, parasitic capacitance, CPAR,
and sampling capacitance, CS, is typically less than 16 pF.
When the SHA goes into track mode, the input source must
charge or discharge the voltage stored on CS to the new input
voltage. This action of charging and discharging CS, averaged
over a period of time and for a given sampling frequency, fS,
makes the input impedance appear to have a benign resistive
component. However, if this action is analyzed within a sampling
period (i.e., T = 1/fS), the input impedance is dynamic and there-
fore certain precautions on the input drive source should be
observed.
The resistive component to the input impedance can be com-
puted by calculating the average charge that gets drawn by CH
from the input drive source. It can be shown that if CS is allowed
to fully charge up to the input voltage before switches QS1 are
opened, then the average current into the input is the same as if
there were a resistor of 1/(CS fS) ohms connected between the
inputs. This means that the input impedance is inversely pro-
portional to the converter’s sample rate. Since CS is only 4 pF,
this resistive component is typically much larger than that of the
drive source (i.e., 25 k
Ω at f
S = 10 MSPS).
If one considers the SHA’s input impedance over a sampling
period, it appears as a dynamic input impedance to the input
drive source. When the SHA goes into the track mode, the input
source should ideally provide the charging current through RON
of switch QS1 in an exponential manner. The requirement of
exponential charging means that the most common input source,
an op amp, must exhibit a source impedance that is both low
and resistive up to and beyond the sampling frequency.
The output impedance of an op amp can be modeled with a
series inductor and resistor. When a capacitive load is switched
onto the output of the op amp, the output will momentarily
drop due to its effective output impedance. As the output recov-
ers, ringing may occur. To remedy the situation, a series resistor
can be inserted between the op amp and the SHA input as shown
in Figure 7. The series resistance helps isolate the op amp from
the switched-capacitor load.
10 F
VINA
VINB
SENSE
AD9221/AD9223/
AD9220
0.1 F
RS
VCC
VEE
RS
VREF
REFCOM
Figure 7. Series Resistor Isolates Switched-Capacitor SHA
Input from Op Amp. Matching Resistors Improve SNR
Performance
The optimum size of this resistor is dependent on several factors,
which include the AD9221/AD9223/AD9220 sampling rate, the
selected op amp, and the particular application. In most applica-
tions, a 30
Ω to 50 Ω resistor is sufficient. However, some
applications may require a larger resistor value to reduce the noise
bandwidth or possibly limit the fault current in an overvoltage
condition. Other applications may require a larger resistor value
as part of an antialiasing filter. In any case, since the THD
performance is dependent on the series resistance and the above
mentioned factors, optimizing this resistor value for a given
application is encouraged.
A slight improvement in SNR performance and dc offset
performance is achieved by matching the input resistance of VINA
and VINB. The degree of improvement is dependent on the
resistor value and the sampling rate. For series resistor values
greater than 100
Ω, the use of a matching resistor is encouraged.
Figure 8 shows a plot for THD performance versus RSERIES for
the AD9221/AD9223/AD9220 at their respective sampling rate
and Nyquist frequency. The Nyquist frequency typically repre-
sents the worst case scenario for an ADC. In this case, a high
speed, high performance amplifier (AD8047) was used as the
buffer op amp. Although not shown, the AD9221/AD9223/AD9220
exhibits a slight increase in SNR (i.e. 1 dB to 1.5 dB) as the
resistance is increased from 0 k
Ω to 2.56 kΩ due to its bandlimiting
effect on wideband noise. Conversely, it exhibits slight decrease
in SNR (i.e., 0.5 dB to 2 dB) if VINA and VINB do not have a
matched input resistance.
RSERIES
–45
–55
–85
1
10k
10
100
1k
–65
–75
AD9220
AD9223
AD9221
Figure 8. THD vs. RSERIES (fIN = fS / 2, AIN = –0.5 dB, Input
Span = 2 V p-p, VCM = 2.5 V)
Figure 8 shows that a small RSERIES between 30
Ω and 50 Ω
provides the optimum THD performance for the AD9220.
Lower values of RSERIES are acceptable for the AD9223 and
AD9221 as their lower sampling rates provide a longer transient
recovery period for the AD8047. Note that op amps with lower
bandwidths will typically have a longer transient recovery period
and therefore require a slightly higher value of RSERIES and/or
lower sampling rate to achieve the optimum THD performance.
As the value of RSERIES increases, a corresponding increase in
distortion is noted. This is due to its interaction with the SHA’s
parasitic capacitor, CPAR, which has a signal dependency. Thus,
the resulting R-C time constant is signal dependent and conse-
quently a source of distortion.
The noise or small-signal bandwidth of the AD9221/AD9223/
AD9220 is the same as their full-power bandwidth as shown in
Figure 2. For noise sensitive applications, the excessive bandwidth
may be detrimental and the addition of a series resistor and/or


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