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ST6369 Arkusz danych(PDF) 10 Page - STMicroelectronics |
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ST6369 Arkusz danych(HTML) 10 Page - STMicroelectronics |
10 / 71 page ST6369 CORE The Core of the ST6369 is implemented inde- pendently from the I/O or memory configuration. Consequently, it can be treated as an independent central processor communicating with I/O and mem- ory via internal addresses, data, and control busses. The in-core communication is arranged as shown in the following block diagram figure; the controller being externally linked to both the reset and the os- cillator, while the core is linked to the dedicated on- chip macrocells peripherals via the serial data bus and indirectly for interrupt purposes through the control registers. Registers The ST6369 Core has five registers and three pairs of flags available to the programmer. They are shown in Figure 4 and are explained in the fol- lowing paragraphs together with the program and data memory page registers. Accumulator (A). The accumulator is an 8-bit general purpose register used in all arithmetic cal- culations, logical operations, and data manipula- tions. The accumulator is addressed in the data space as RAM location at the FFH address. Accordingly, the ST6369 instruction set can use the accumulator as any other register of the data space. Figure 3. Core Block Diagram SHORT DIRECT ADDRESSING MODE V REGISTER W REGISTER PROGRAM COUNTER SIX LEVELS STACK REGISTER C C C Z Z Z NOR MAL FLAGS INTERRUPT FLAGS NMI FLAGS INDEX REGISTER VA000423 b7 b7 b7 b7 b7 b0 b0 b0 b0 b0 b0 b11 ACCUMULATOR Y REG. POINTER X REG. POINTER Figure 4. Core Programming Model ® ST6369 6/67 |
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