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ST70136G Arkusz danych(PDF) 11 Page - STMicroelectronics |
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ST70136G Arkusz danych(HTML) 11 Page - STMicroelectronics |
11 / 24 page ST70136 11/24 4.7.1.3 - Special Features Configuration This register is located at the address “010” and is used to configure different blocks. 4.7.1.4 - VCXO Control 4.7.1.5 - Test Only Registers They are presently located at address “100” to “101”. 4.7.1.6 - Tone Detection Threshold Setting Register 4.7.1.7 - Status Register & tone detector This register can be used in the case of read / write registers. Note: 1. R/W_clear: bit is resetted to 0 by writing 0. Table 4 : Adsl Configuration (address [b2:b0]=”010”) Name Pos. Type Def. Description Reserved 14.13 R/W 00 Reserved VCO-DAC 12 R/W 1 Enable the VCO DAC 1: enabled 0: disabled Other 11.4 R/W 0..0 Reserved FVCXO 3 R/W 0 Filtered VCXO output 1 : filtered 0 : not filtered Table 5 : VCXO DAC Value (address [b2:b0]=”011”) Name pos. type def. Description DAC value 14..7 R/W 80H 8 bits for VCO DAC. 0...0 = min. current 1...1 = max current. Others 6..3 R/W 0000 Reserved Table 6 : Tone Detection Threshold Setting Register (address [b2:b0]=”110”) Name Pos. Type Def. Description Threshold Level 14..5 R/W 1000000000 Set the threshold of the tone detector Reserved 4.3 R/W 00 Reserved Table 7 : Status & Tone Detector Register (address [b2:b0]=”111”) Name Pos. Type Def. Description Receiver Clip indicator 14 R/W_clear 1 0 1: Receive Clipping occurred Transceiver Clip indicator 13 R/W_clear 0 1: Transmit Clipping occurred Sleeping Mode 12 R/W 0 0: disable tone detector in power down 1: enable tone detector in power down Tone Detector 11 R/W 0 Tone detector frequency setting 0: standard ADSL (tone 40) 1: ADSL over ISDN (tone 72) Debug Mode 10 R/W 0 When in normal mode “0” the CTRLOUT pin is in HIZ and don’t care for R/W and the control access register are always writing operation whatever on R/W pin. When in debug mode “1” the CTRLOUT and R/W pins are operating as defined in pin description chapter. Software Reset 9 R/W 0 When set all registers are set to their default value Reserved 8..3 R/W 0..0 Reserved |
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