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ST7LITE29 Arkusz danych(PDF) 7 Page - STMicroelectronics |
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ST7LITE29 Arkusz danych(HTML) 7 Page - STMicroelectronics |
7 / 131 page ST7LITE2 7/131 PIN DESCRIPTION (Cont’d) Legend / Abbreviations for Table 1: Type: I = input, O = output, S = supply In/Output level: CT= CMOS 0.3VDD/0.7VDD with input trigger Output level: HS = 20mA high sink (on N-buffer only) Port and control configuration: – Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog – Output: OD = open drain, PP = push-pull The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state. Table 1. Device Pin Description Pin No. Pin Name Level Port / Control Main Function (after reset) Alternate Function Input Output 116 VSS S Ground 217 VDD S Main power supply 3 18 RESET I/O CT XX Top priority non maskable interrupt (active low) 4 19 PB0/AIN0/SS I/O CT X ei3 XX X Port B0 ADC Analog Input 0 or SPI Slave Select (active low) 5 20 PB1/AIN1/SCK I/O CT X XX X Port B1 ADC Analog Input 1 or SPI Se- rial Clock 6 1 PB2/AIN2/MISO I/O CT X XX X Port B2 ADC Analog Input 2 or SPI Master In/ Slave Out Data 7 2 PB3/AIN3/MOSI I/O CT X ei2 XX X Port B3 ADC Analog Input 3 or SPI Master Out / Slave In Data 8 3 PB4/AIN4/CLKIN I/O CT X XX X Port B4 ADC Analog Input 4 or Exter- nal clock input 9 4 PB5/AIN5 I/O CT X XX X Port B5 ADC Analog Input 5 10 5 PB6/AIN6 I/O CT X XX X Port B6 ADC Analog Input 6 11 6 PA7 I/O CT HS X ei1 X X Port A7 12 7 PA6 /MCO/ ICCCLK/BREAK I/O CT X ei1 XX Port A6 Main Clock Output or In Circuit Communication Clock or Ex- ternal BREAK Caution: During reset, this pin must be held at high level to avoid entering ICC mode un- expectedly (this is guaranteed by the internal pull-up if the ap- plication leaves the pin float- ing). 1 |
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