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ADS7229 Arkusz danych(PDF) 7 Page - Texas Instruments |
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ADS7229 Arkusz danych(HTML) 7 Page - Texas Instruments |
7 / 46 page TIMING CHARACTERISTICS (1) (2): 5V ADS7229 ADS7230 www.ti.com........................................................................................................................................................................................................ SBAS437 – MAY 2008 All specifications typical at –40 °C to +85°C and +VA = +VBD = 5V, unless otherwise noted. ADS7229, ADS7230 PARAMETER MIN TYP MAX UNIT External, 0.5 21 fCCLK = 1/2 fSCLK fCCLK Frequency, conversion clock, CCLK MHz Internal, 21 23 24.5 fCCLK = 1/2 fSCLK t1 Setup time, falling edge of CS to EOC 1 CCLK t2 Hold time, falling edge of CS to EOC 0 ns tCL Pulse duration, CONVST low 40 ns t3 Hold time, falling edge of CS to EOS 20 ns t4 Setup time, rising edge of CS to EOS 20 ns t5 Hold time, rising edge of CS to EOS 20 ns Setup time, falling edge of CS to first falling t6 5 ns SCLK tSCLKL Pulse duration, SCLK low 8 tSCLK – 8 ns tSCLKH Pulse duration, SCLK high 8 tSCLK – 8 ns I/O clock only 20 I/O and conversion clock 23.8 2000 tSCLK Cycle time, SCLK ns I/O clock, chain mode 20 I/O and conversion clock, 23.8 2000 chain mode tH2 Hold time, falling edge of SCLK to SDO invalid 10pF Load 2 ns tD1 Delay time, falling edge of SCLK to SDO valid 10pF Load 10 ns Delay time, falling edge of CS to SDO valid, tD2 10pF Load 8.5 ns SDO MSB output tS1 Setup time, SDI to falling edge of SCLK 8 ns tH1 Hold time, SDI to falling edge of SCLK 4 ns Delay time, rising edge of CS/FS to SDO tD3 tD3 5 ns 3-state Setup time, 16th falling edge of SCLK before t7 10 ns rising edge of CS/FS (1) All input signals are specified with tr = tf = 1.5ns (10% to 90% of VBD) and timed from a voltage level of (VIL + VIH)/2. (2) See timing diagrams. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): ADS7229 ADS7230 |
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Podobny opis - ADS7229 |
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