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AD5751 Arkusz danych(PDF) 7 Page - Analog Devices |
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AD5751 Arkusz danych(HTML) 7 Page - Analog Devices |
7 / 22 page Preliminary Technical Data AD5751 Rev. PrA | Page 7 of 22 t8 0 ns min Data hold time t10 , t9 1 μs max CLEAR pulse high/low activation time t11 200 ns min Minimum SYNC high time (READ MODE) t12 25 ns max SCLK rising edge to SDO valid (SDO CL=20pf ) t13 1 us max CLEAR pulse low activation time 1 Guaranteed by characterization. Not production tested. 2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. 200µA IOL 200µA IOH VOH(min)-VOL(max) TO OUTPUT PIN CL 15pF 2 SDO Load Timing. |
Podobny numer części - AD5751 |
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