ADL5502ACBZ-P7 datasheet(4/14 Pages) AD

Numer części	ADL5502ACBZ-P7

Szczegółowy opis	800 MHz to 3800 MHz Crest Factor Detector

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ADL5502

Preliminary Technical Data

Rev. PrD (04/20/2008) | Page 4 of 14

Parameter

Condition

Min

Typ

Max

Unit

RMS CONVERSION (f = 3500 MHz)

Input RFIN to output VRMS

Input Impedance

TBD||TBD

Ω||pF

Dynamic Range1

CW input, −40°C < TA < +85°C

±0.25 dB Error2

VS = 3 V

15

dB

±1 dB Error3

VS = 3 V

25

dB

±2 dB Error3

VS = 3 V

30

dB

Maximum Input Level

±0.25 dB error

TBD

dBm

Minimum Input Level

±1 dB error

TBD

dBm

Conversion Gain

VRMS = (Gain × VIN) + Intercept

1.33

V/V rms

Output Intercept4

–0.005

V

Output Voltage—High Power In

PIN = +5 dBm, 400 mV rms

TBD

V

Output Voltage—Low Power In

PIN = −21 dBm, 20 mV rms

TBD

V

VRMS OUTPUT

Pin VRMS

Output Offset

No signal at RFIN

150

mV

Response time

5 dB Step, 10% to 90% of settling level, no

filter cap

15

μS

Available Output Current

3

mA

VENV OUTPUT

Pin VENV

Envelope Modulation Bandwidth

5

10

MHz

Maximum Output Voltage

Vs = 2.7 V, RLOAD ≥ 10 kΩ

1.5

V

Output Offset

No signal at RFIN

TBD

mV

Response time

5 dB Step, 10% to 90% of settling level, no

filter cap

TBD

μS

Available Output Current

3

mA

PEAK HOLD

Hold Time

100

200

μS

Hold Voltage Drop

TBD

mV/ μS

CONTROL INTERFACE

Logic Level to, Real Time Envelope, HI

2.7 V ≤ VS ≤ 3.5 V, −40°C < TA < +85°C

1.8

VPOS

V

Input Current when HI

2.7 V at ENBL, –40°C ≤ TA ≤ +85°C

0.05

0.1

μA

Logic Level for Peak Hold Condition, LO

2.7 V ≤ VS ≤ 3.5 V, −40°C < TA < +85°C

–0.5

+0.5

V

Enable Time

CFLTR = Open, 0 dBm at RFIN

TBD

μs

Disable Time

CFLTR = 100 nF, 0 dBm at RFIN

TBD

μs

ENABLE INTERFACE

Pin ENBL

Logic Level to Enable Power, HI Condition

2.5 V ≤ VS ≤ 3.5 V, −40°C < TA < +85°C

1.8

VPOS

V

Input Current when HI

2.5 V at ENBL, –40°C ≤ TA ≤ +85°C

0.05

0.1

μA

Logic Level to Disable Power, LO Condition

2.5 V ≤ VS ≤ 3.5 V, −40°C < TA < +85°C

–0.5

+0.5

V

Power-Up Response Time5

CFLTR = Open, 0 dBm at RFIN

TBD

μs

CFLTR = 100 nF, 0 dBm at RFIN

TBD

μs

POWER SUPPLIES

Operating Range

−40°C < TA < +85°C

2.5

3.5

V

Quiescent Current

No signal at RFIN6

5.0

mA

Disable Current

ENBL in LO Condition, no signal at RFIN

< TBD

5

μA

1 The available output swing, and hence the dynamic range, is altered by the supply voltage; see TBD.

2 Error referred to delta from 25°C response.

3 Error referred to best-fit line at 25°C

4 Calculated using linear regression.

5 The response time is measured from 10% to 90% of settling level

6 Supply current is input level dependant; see TBD.

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