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ADUC7036 Arkusz danych(PDF) 7 Page - Analog Devices |
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ADUC7036 Arkusz danych(HTML) 7 Page - Analog Devices |
7 / 140 page Preliminary Technical Data ADuC7036 Rev. Pr.A | Page 7 of 140 Parameter Test Conditions/Comments Min Typ Max Unit From MCU Power-Down Oscillator Running Wake Up from Interrupt 2 ms Wake Up from LIN 2 ms Crystal Powered Down Wake Up from Interrupt 500 ms Internal PLL Lock Time 1 ms LIN INPUT/OUTPUT GENERAL Baud Rate 1000 20,000 Bits/sec VDD Supply voltage range at which the LIN interface is functional 7 18 V Input Capacitance 5.5 pF Input Leakage Current Input (low) = IO_VSS −800 −400 µA LIN Comparator Response Time1 Using 22 Ω resistor 38 90 µs ILIN DOM MAX Current limit for driver when LIN bus is in dominant state, VBAT = VBAT (MAX) 40 200 mA ILIN_PAS_REC Driver off; 7.0 V < VLIN < 18 V; VDD = VLIN − 0.7 V −20 +20 µA ILIN1 VBAT disconnected, VDD = 0 V, 0 < VLIN < 18 V 10 µA ILIN_PAS_DOM1 Input leakage VLIN = 0 V −1 mA ILIN_NO_GND29 Control unit disconnected from ground, GND = VDD; 0 V < VLIN < 18 V; VBAT = 12 V −1 +1 mA VLIN_DOM1 LIN receiver dominant state, VDD > 7.0 V 0.4 VDD V VLIN_REC1 LIN receiver recessive state, VDD > 7.0 V 0.6 VDD V VLIN_CNT1 LIN receiver center voltage, VDD > 7.0 V 0.475 VDD 0.5 VDD 0.525 VDD V VHYS1 LIN receiver hysteresis voltage 0.175 VDD V VLIN_DOM_DRV_LOSUP1 LIN dominant output voltage, VDD = 7 V RL 500 Ω 1.2 V RL 1000 Ω 0.6 V VLIN_DOM_DRV_HISUP1 LIN dominant output voltage, VDD = 18 V RL 500 Ω 2 V RL 1000 Ω 0.8 V VLIN_RECESSIVE LIN recessive output voltage 0.8 VDD V VBAT Shift29 0 0.1 VDD V GND Shift29 0 0.1 VDD V RSLAVE Slave termination resistance 20 30 47 kΩ VSERIAL DIODE29 Voltage drop at the Serial Diode DSer_Int 0.4 0.7 1 V Symmetry of Transmit Propagation Delay1 VDD (MIN) = 7 V −2 +2 µs Receive Propagation Delay1 VDD (MIN) = 7 V 6 µs Symmetry of Receive Propagation Delay1 VDD (MIN) = 7 V −2 +2 µs LIN VERSION 2.0 SPECIFICATION Bus load conditions (CBUS||RBUS): 1 nF||1 kΩ; 6.8 nF||660 Ω; 10 nF||500 Ω D1 Duty Cycle 1, THREC(MAX) = 0.744 × VBAT, THDOM(MAX) = 0.581 × VBAT, VSUP = 7.0 V . . . 18 V; tBIT = 50 µs, D1 = tBUS_REC(MIN)/(2 × tBIT) 0.396 D2 Duty Cycle 2, THREC(MIN) = 0.284 × VBAT, THDOM(MIN) = 0.422 × VBAT, VSUP = 7.0 V . . . 18 V; tBIT = 50 µs, D2 = tBUS_REC(MAX)/(2 × tBIT) 0.581 BSD INPUT/OUTPUT30 Baud Rate 1164 1200 1236 Bits/sec |
Podobny numer części - ADUC7036 |
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Podobny opis - ADUC7036 |
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