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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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TS87C51U2 Arkusz danych(PDF) 2 Page - TEMIC Semiconductors |
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TS87C51U2 Arkusz danych(HTML) 2 Page - TEMIC Semiconductors |
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2 / 67 page  2 Rev. C - Aug. 24, 1999 TS80C51U2 TS83C51U2 TS87C51U2 and (pin28 or pin34) of 44-pin package (see Pin configuration). UART_1 is fully compliant with the first one allowing an internal baud rate generator to be the clock source. This common internal baud rate generator can be used independently by each UART or both as clock source allowing to program various speeds. The TS80C51U2 provides 7 sources of interrupt with four priority levels. UART_1 has a lower priority than Timer 2. The Serial Ports are full duplex meaning they can transmit and receive simultaneously. They are also receive buffered, meaning they can start reception of a second byte before a previously received byte has been read from the receive register. The Serial Port receive and transmit registers of UART_1 are both accessed at Special Function Register SBUF_1. Writing to SBUF_1 loads the transmit register and reading SBUF_1 accesses a physical separate receive register. The UART_1 port control and status is the Special Function Register SCON_1. This register contains not only the mode selection bit but also the 9th bit for transmit and receive (TB8_1 and RB8_1) and the serial port interrupt bits (TI_1 and RI_1). The automatic address recognition feature is enabled when multiprocessor communication is enabled. Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the Serial Port to examine address of each incoming frame and provides filtering capability. The UART_1 also comes with Frame error detection, similar to the UART_0. |
Podobny numer części - TS87C51U2 |
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Podobny opis - TS87C51U2 |
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