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M4Z32-BR00SH1 Arkusz danych(PDF) 9 Page - STMicroelectronics |
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M4Z32-BR00SH1 Arkusz danych(HTML) 9 Page - STMicroelectronics |
9 / 25 page M40Z300, M40Z300W Operation 9/25 2 Operation The M40Z300/W, as shown in Figure 5 on page 8, can control up to four (eight, if placed in parallel) standard low-power SRAMs. These SRAMs must be configured to have the chip enable input disable all other input signals. Most slow, low-power SRAMs are configured like this, however many fast SRAMs are not. During normal operating conditions, the conditioned chip enable (E1CON to E4CON) output pins follow the chip enable (E) input pin with timing shown in Figure 6 on page 10 and Table 7 on page 17. An internal switch connects VCC to VOUT. This switch has a voltage drop of less than 0.3V (IOUT1). When VCC degrades during a power failure, E1CON to E4CON are forced inactive independent of E. In this situation, the SRAM is unconditionally write protected as VCC falls below an out-of-tolerance threshold (VPFD). For the M40Z300 the power fail detection value associated with VPFD is selected by the Threshold Select (THS) pin and is shown in Table 6 on page 15. For the M40Z300W, the THS pin selects both the supply voltage and VPFD (also shown in Table 6 on page 15). Note: In either case, THS pin must be connected to either VSS or VOUT. If chip enable access is in progress during a power fail detection, that memory cycle continues to completion before the memory is write protected. If the memory cycle is not terminated within time tWPT, E1CON to E4CON are unconditionally driven high, write protecting the SRAM. A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the SRAM's contents. At voltages below VPFD (min), the user can be assured the memory will be write protected within the Write Protect Time (tWPT) provided the VCC fall time exceeds tF (see Figure 6 on page 10). As VCC continues to degrade, the internal switch disconnects VCC and connects the internal battery to VOUT. This occurs at the switchover voltage (VSO). Below the VSO, the battery provides a voltage VOHB to the SRAM and can supply current IOUT2 (see Table 6 on page 15). When VCC rises above VSO, VOUT is switched back to the supply voltage. Outputs E1CON to E4CON are held inactive for tCER (120ms maximum) after the power supply has reached VPFD, independent of the E input, to allow for processor stabilization (see Figure 10 on page 16). |
Podobny numer części - M4Z32-BR00SH1 |
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Podobny opis - M4Z32-BR00SH1 |
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