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ADP2503ACPZ-4.2-R71 Arkusz danych(PDF) 10 Page - Analog Devices |
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ADP2503ACPZ-4.2-R71 Arkusz danych(HTML) 10 Page - Analog Devices |
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10 / 16 page  ADP2503/ADP2504 Preliminary Technical Data THEORY OF OPERATION 1.0µH 22µF BAND GAP REFERENCE SYNC PGND AGND EN PVIN VBAT = 2.3V TO 5.5V VIN VOUT SW1 SW2 EN 2.25V UVLO 10µF ADP2503/ADP2504 BIASING ADP2503/ADP2504 PMOS1 PMOS2 NMOS1 NMOS2 THERMAL PROTECTION PWM CONTROL OSCILLATOR 8 4 5 6 7 3 9 FB –0.5V 2 1 10 CS SOFT START Figure 27. ADP2503/ADP2504 Block Diagram The ADP2503/ADP2504 are synchronous average current- mode switching buck-boost regulators designed to maintain a fixed output voltage VOUT from an input supply VIN that can be above, equal to, or below VOUT. When VIN is significantly greater than VOUT, the device is in buck mode: PMOS2 is always active, NMOS2 is always off and the switches PMOS1, NMOS1 consti tute a buck converter. When VIN is significantly lower than VOUT, the device is in boost mode: PMOS1 is always active, NMOS1 is always off and the switches NMOS2, PMOS2 constitute a boost converter. When VIN is in the range [VOUT − 10%; VOUT + 10%], the ADP2503/ADP2504 automatically enter the buck-boost mode. In buck-boost mode, the two operations buck (PMOS1 and NMOS1 switching in antiphase) and boost (NMOS2 and PMOS2 switching in antiphase) take place at each period of the clock. This is aimed at maintaining the regulation and keeping a minimal current ripple in the inductor to guarantee good transient performances. REVERSE CURRENT LIMIT In case of a short circuit on VOUT to a value greater than expected, the inductor current becomes negative (reverse current). The negative peak value is limited to 1.1 A by deactivating the switch PMOS2. POWER SAVE MODE When the SYNC pin is low, the ADP2503/ADP2504 can operate in power save mode (PSM). In this mode, when the load current becomes lower than 75 mA nominally at VIN = 3.6 V, the controller pulls up VOUT and then halts the switching regime until VOUT goes back to a restart value. Then VOUT is pulled up again for a new cycle. This minimizes the switching losses at light load. When the load rises above 150 mA, the ADP2503/ADP2504 revert back to fixed PWM mode. This results in about 75 mA of hysteresis between PSM and fixed PWM, preventing oscillations between these two modes. SOFT START When the ADP2503/ADP2504 are started, VOUT is ramped from 0 V to its final programmed value in 200 μs (typ). This limits the inrush current to less than 600 mA for a nominal output capacitor of 20 μF. Because the VOUT start-up slope is constant, the inrush current becomes larger if the output capacitor is made larger. Rev. PrB | Page 10 of 16 |
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