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DAC6311IDCKR Arkusz danych(PDF) 6 Page - Texas Instruments |
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DAC6311IDCKR Arkusz danych(HTML) 6 Page - Texas Instruments |
6 / 40 page SERIAL WRITE OPERATION SCLK 1 16 SYNC D IN DB15 DB0 DB15 t 10 t 6 t 3 t 2 t 1 t 7 t 9 t 5 t 4 t 8 TIMING REQUIREMENTS (1) DAC5311 DAC6311 DAC7311 SBAS442 – AUGUST 2008 ................................................................................................................................................................................................ www.ti.com All specifications at –40°C to +125°C, and AVDD = +1.8V to +5.5V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AVDD = 1.8V to 3.6V 50 t1 (2) SCLK cycle time ns AVDD = 3.6V to 5.5V 20 AVDD = 1.8V to 3.6V 25 t2 SCLK high time ns AVDD = 3.6V to 5.5V 10 AVDD = 1.8V to 3.6V 25 t3 SCLK low time ns AVDD = 3.6V to 5.5V 10 AVDD = 1.8V to 3.6V 0 t4 SYNC to SCLK rising edge setup time ns AVDD = 3.6V to 5.5V 0 AVDD = 1.8V to 3.6V 5 t5 Data setup time ns AVDD = 3.6V to 5.5V 5 AVDD = 1.8V to 3.6V 4.5 t6 Data hold time ns AVDD = 3.6V to 5.5V 4.5 AVDD = 1.8V to 3.6V 0 t7 SCLK falling edge to SYNC rising edge ns AVDD = 3.6V to 5.5V 0 AVDD = 1.8V to 3.6V 50 t8 Minimum SYNC high time ns AVDD = 3.6V to 5.5V 20 AVDD = 1.8V to 3.6V 100 t9 16th SCLK falling edge to SYNC falling edge ns AVDD = 3.6V to 5.5V 100 AVDD = 1.8V to 3.6V 15 SYNC rising edge to 16th SCLK falling edge t10 ns (for successful SYNC interrupt) AVDD = 3.6V to 5.5V 15 (1) All input signals are specified with tR = tF = 3ns (10% to 90% of AVDD) and timed from a voltage level of (VIL + VIH)/2. (2) Maximum SCLK frequency is 50MHz at AVDD = 3.6V to 5.5V and 20MHz at AVDD = 1.8V to 3.6V. 6 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DAC5311 DAC6311 DAC7311 |
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