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FAN5632 Arkusz danych(PDF) 3 Page - Fairchild Semiconductor |
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FAN5632 Arkusz danych(HTML) 3 Page - Fairchild Semiconductor |
3 / 13 page © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5631/FAN5632 Rev. 1.0.2 3 Pin Configuration VIN VOUT NC NC NC CB+ CB- GND VSEL EN 10 9 6 7 8 1 2 3 4 5 Top View Figure 3. Pin Assignments Pin Definitions Pin # Name Description 1 VSEL Output Voltage Select Logic Input Pin. The VSEL pin cannot be left floating and must be connected to either a logic high or logic low level. FAN5631: If a logic low is applied to the VSEL pin, VOUT is 1.2V; if a logic high is applied, VOUT is 1.5V. FAN5632: If a logic low is applied to the VSEL pin, the efficiency optimization mode is enabled and the output voltage accuracy is relaxed to meet optimum efficiency. If a logic high is applied, the device operates like a typical charge pump converter. 2 EN Enable Input Pin. If a logic high is applied to the EN pin, the device is enabled. If a logic low is applied, the device is disabled and the supply current is reduced to less than 1µA. The EN pin cannot be left floating and must be connected to a logic high or logic low level. 3 CB+ Bucket Capacitor Positive Pin. 4 GND Ground Pin. This pin is connected to the internal MOSFET switches. This pin must be externally connected to GND. 5 CB- Bucket Capacitor Negative Pin. 6 VOUT Output Voltage Pin. 7 NC Not Connected. This pin is not internally connected. 8 NC Not Connected. This pin is not internally connected. 9 VIN Supply Voltage Input. 10 NC Not Connected. This pin is not internally connected. |
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