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ADS62P22IRGCT Arkusz danych(PDF) 7 Page - Texas Instruments |
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ADS62P22IRGCT Arkusz danych(HTML) 7 Page - Texas Instruments |
7 / 71 page www.ti.com DIGITAL CHARACTERISTICS (1) ADS62P25, ADS62P24 ADS62P23, ADS62P22 SLAS576A – OCTOBER 2007 – REVISED FEBRUARY 2008 ELECTRICAL CHARACTERISTICS (continued) Typical values are at 25 °C, AVDD = 3.3 V, DRVDD = 1.8 V to 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, applies to CMOS and LVDS interfaces, unless otherwise noted. Min and max values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.3 V, DRVDD = 3.3 V, unless otherwise noted. ADS62P25 ADS62P24 ADS62P23 ADS62P22 FS = 125 MSPS FS = 105 MSPS FS = 80 MSPS FS = 65 MSPS PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX IMD 2-Tone F1 = 185 MHz, F2 = 190 MHz 88 87 92 92 dBFS Intermodulation each tone at -7 dBFS Distortion Crosstalk Up to 100 MHz 95 95 95 95 dB Recovery to within 1% (of final Input Overload clock value) for 6-dB overload with sine 1 1 1 1 Recovery cycles wave input PSRR AC Power for 100 mVpp signal on AVDD 35 35 35 35 dBc Supply supply Rejection Ratio The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1 AVDD = 3.0 V to 3.6 V. ADS62P25/ADS62P24 PARAMETER TEST CONDITIONS ADS62P23/ADS62P22 MIN TYP MAX UNIT DIGITAL INPUTS RESET, CTRL1, CTRL2, CTRL3, SCLK, SDATA, SEN (2)(3) High-level input voltage 2.4 V Low-level input voltage 0.8 V High-level input current 33 µA Low-level input current –33 µA Input capacitance 4 pF DIGITAL OUTPUTS CMOS INTERFACE, DRVDD = 1.65 V to 3.6 V High-level output voltage DRVDD V Low-level output voltage 0 V Output capacitance inside the device, from Output capacitance 2 pF each output to ground DIGITAL OUTPUTS LVDS INTERFACE, DRVDD = 3.0 V to 3.6 V, IO = 3.5 mA, RL = 100 Ω (4) High-level output voltage 1375 mV Low-level output voltage 1025 mV Output differential voltage, |VOD| 225 350 mV VOS Output offset voltage, single-ended Common-mode voltage of OUTP, OUTM 1200 mV Output capacitance inside the device, from Output capacitance 2 pF either output to ground (1) All LVDS and CMOS specifications are characterized, but not tested at production. (2) SCLK and SEN function as digital input pins when they are used for serial interface programming. When used as parallel control pins, analog voltage needs to be applied as per Table 2 and Table 3. (3) All digital input pins are referred to AVDD supply. (4) IO refers to the LVDS buffer current setting, RL is the differential load resistance between the LVDS output pair. Copyright © 2007–2008, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): ADS62P25, ADS62P24 ADS62P23, ADS62P22 |
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