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AD9228BCPZRL7-65 Arkusz danych(PDF) 3 Page - Analog Devices |
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AD9228BCPZRL7-65 Arkusz danych(HTML) 3 Page - Analog Devices |
3 / 52 page AD9228 Rev. B | Page 3 of 52 SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 1. AD9228-40 AD9228-65 Parameter1 Temperature Min Typ Max Min Typ Max Unit RESOLUTION 12 12 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full ±1 ±8 ±1 ±8 mV Offset Matching Full ±2 ±8 ±2 ±8 mV Gain Error Full ±0.4 ±1.2 ±2 ±3.5 % FS Gain Matching Full ±0.3 ±0.7 ±0.3 ±0.7 % FS Differential Nonlinearity (DNL) Full ±0.25 ±0.5 ±0.3 ±0.65 LSB Integral Nonlinearity (INL) Full ±0.4 ±1 ±0.4 ±1 LSB TEMPERATURE DRIFT Offset Error Full ±2 ±2 ppm/°C Gain Error Full ±17 ±17 ppm/°C Reference Voltage (1 V Mode) Full ±21 ±21 ppm/°C REFERENCE Output Voltage Error (VREF = 1 V) Full ±2 ±30 ±2 ±30 mV Load Regulation at 1.0 mA (VREF = 1 V) Full 3 3 mV Input Resistance Full 6 6 kΩ ANALOG INPUTS Differential Input Voltage (VREF = 1 V) Full 2 2 V p-p Common-Mode Voltage Full AVDD/2 AVDD/2 V Differential Input Capacitance Full 7 7 pF Analog Bandwidth, Full Power Full 315 315 MHz POWER SUPPLY AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V IAVDD Full 155 170 232 245 mA IDRVDD Full 31 34 34 38 mA Total Power Dissipation (Including Output Drivers) Full 335 367 478 510 mW Power-Down Dissipation Full 2 5.8 2 5.8 mW Standby Dissipation2 Full 72 72 mW CROSSTALK Full −100 −100 dB CROSSTALK (Overrange Condition)3 Full −100 −100 dB 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Can be controlled via the SPI. 3 Overrange condition is specific with 6 dB of the full-scale input range. |
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