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TDA7427AAD Arkusz danych(PDF) 10 Page - STMicroelectronics |
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TDA7427AAD Arkusz danych(HTML) 10 Page - STMicroelectronics |
10 / 21 page The negative input is switchable to three input pins ( LPIN 1, LPIN 2 and LPIN 3) to increase the flexibility in application. This feature allows two separate active filters for different applications A logical ”1” in the LPIN 1/2 register activates pin LPIN 1, otherwise pin LPIN 2 is active. While the high current mode is activated LPIN 3 is switched on. INLOCK DETECTOR The charge pump can be switched in low current mode either via software or automatically by the inlock detector by setting bit LDENA to ”1”. The charge pump is forced in low current mode when a phase difference of 10-40 µsec is reached. A phase difference larger then the programmed values will switch the charge pump immediately in the high current mode. Programmable delays are available for inlock de- tection. IF COUNTER SYSTEM (AM/FM/AM - UPC MODES) The if counter works in modes controlled by IFCM register (see table): IFCM1 IFCM0 FUNCTION 0 0 NOT USED 0 1 FM MODE 1 0 AM MODE 11 10.7MHz AM UP CONVERSION MODE Typical input impedance for IF inputs is 4K Ω. A sample timer to generate the gate signal for the main counter is build with a 14-bit programmable counter to have the possibility to use any crystal oscillator frequency. In FM mode 6.25KHz in AM mode a 1KHz signal is generated. This is followed by an asynchronous divider to generate different sampling times (see fig. 4). Intermediate Frequency Main Counter This counter is a 11/21 bits synchronous autore- load down-counter. Four bits are programmable to have the possibility for an adjust to the fre- quency of the CF filter. The counter length is automatically adjusted to the chosen sampling time and the counter mode (AM, FM, AM-UPC). At the start the counter will be loaded with a de- fined value which is an equivalent to the divider value (tsample ⋅ fIF). If a correct frequency is applied to the IF counter frequency inputs IF-AM IF-FM, at the end of the sampling time the main counter is changing its state from 0 H to 1FFFFFH. This is detected by a control logic. The frequency range inside which a successful count results is detected is adjustable by bits EW 0,1,2. Adjustment of the Measurement Sequence Time The precision of the measurements is adjustable by controlling the discrimination window . This is adjustable by programming the control registers EW0...EW2. The measurement time per cycle is adjustable by setting the Register IFS0 - IFS2. Adjust of the Frequency Value The center frequency of the discrimination win- dow is adjustable by the control register ”CF0” to ”CF4”. (see data byte specification). Port Extension and additional functions Five digital open collector outputs and one digital push-pull output are available in application mode. This digital ports are controlled by the data bits DOUT1-DOUT6. D95AU378 tHIGH tR tLOW tR SCL SDA IN SDA OUT tSU-STA tHD-STA tHD-DAT tSD-DAT tSUBTOP ttxt tAA tDH Figure 5. I 2C Bus timing diagram TDA7427A 10/21 |
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