TDA7466 datasheet(7/21 Pages) STMICROELECTRONICS

Numer części	TDA7466

Szczegółowy opis	DIGITALLY CONTROLLED AUDIO PROCESSOR WITH SRS SURROUND SOUND AND VOICE CANCELLER

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I

2C BUS INTERFACE

Data transmission from microprocessor to the

TDA7466 and viceversa takes place through the

2 wires I

2C BUS interface, consisting of the two

lines SDA and SCL (pull-up resistors to positive

supply voltage must be connected).

Data Validity

As shown in fig. 3, the data on the SDA line must

be stable during the high period of the clock. The

HIGH and LOW state of the data line can only

change when the clock signal on the SCL line is

LOW.

Start and Stop Conditions

As shown in fig.4 a start condition is a HIGH to

LOW transition of the SDA line while SCL is

HIGH. The stop condition is a LOW to HIGH tran-

sition of the SDA line while SCL is HIGH.

Byte Format

Every byte transferred on the SDA line must con-

tain 8 bits. Each byte must be followed by an ac-

knowledge bit. The MSB is transferred first.

Acknowledge

The master (

µP) puts a resistive HIGH level on the

SDA line during the acknowledge clock pulse (see

fig. 5). The peripheral (audioprocessor) that ac-

knowledges has to pull-down (LOW) the SDA line

during this clock pulse.

The audioprocessor which has been addressed

has to generate an acknowledge after the recep-

tion of each byte, otherwise the SDA line remains

at the HIGH level during the ninth clock pulse

time. In this case the master transmitter can gen-

erate the STOP information in order to abort the

transfer.

Transmission without Acknowledge

Avoiding to detect the acknowledge of the audio-

processor, the

µP can use a simpler transmission:

simply it waits one clock without checking the

slave acknowledging, and sends the new data.

This approach of course is less protected from

misworking.

Figure 3: Data Validity on the I

2CBUS

Figure 4: Timing Diagram of I

2CBUS

Figure 5: Acknowledge on the I

2CBUS

TDA7466

7/21

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