AD7356

Rev. 0 | Page 7 of 20

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

REFGND

AGND

7

8

16

15

14

13

12

11

SCLK

AGND

DGND

AD7356

TOP VIEW

(Not to Scale)

10

9

CS

Figure 2. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 2

Analog Inputs of ADC A. These analog inputs form a fully differential pair.

3, 6

Reference Decoupling Capacitor Pins. Decoupling capacitors are connected between these pins and the

REFGND pin to decouple the reference buffer for each respective ADC. It is recommended to decouple each

reference pin with a 10 μF capacitor. Provided the output is buffered, the on-chip reference can be taken from

these pins and applied externally to the rest of the system. The nominal internal reference voltage is 2.048 V

and appears at these pins. These pins can also be overdriven by an external reference. The input voltage range

4

REFGND

Reference Ground. This is the ground reference point for the reference circuitry on the AD7356. Refer any

external reference signal to this REFGND voltage. Decoupling capacitors must be placed between this pin and

5, 11

AGND

Analog Ground. This is the ground reference point for all analog circuitry on the AD7356. All analog input

signals should be referred to this AGND voltage. The AGND and DGND voltages should ideally be at the same

potential and must not be more than 0.3 V apart, even on a transient basis.

7, 8

Analog Inputs of ADC B. These analog inputs form a fully differential pair.

9

capacitor in parallel with a 10 μF tantalum capacitor.

10

CS

Chip Select. Active low logic input. This input provides the dual functions of initiating conversions on the

AD7356 and framing the serial data transfer.

12

DGND

Digital Ground. This is the ground reference point for all digital circuitry on the AD7356. Connect this pin to

the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must

not be more than 0.3 V apart, even on a transient basis.

13, 14

Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out

on the falling edge of the SCLK input. To access the 12 bits of data from the AD7356, 14 SCLK falling edges are

required. The data simultaneously appears on both data output pins from the simultaneous conversions of

both ADCs. The data stream consists of two leading zeros followed by the 12 bits of conversion data. The data

is provided MSB first. If CS is held low for 16 SCLK cycles rather than 14 on the AD7356, then two trailing zeros

data from the other ADC follows on the SDATA pins. This allows data from a simultaneous conversion on both

A

15

SCLK

Serial Clock. Logic input. A serial clock input provides the serial clock for accessing the data from the AD7356.

This clock is also used as the clock source for the conversion process.

16

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates.

DGND with a 0.1 μF capacitor in parallel with a 10 μF tantalum capacitor.