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ADS5482 Arkusz danych(PDF) 7 Page - Texas Instruments |
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ADS5482 Arkusz danych(HTML) 7 Page - Texas Instruments |
7 / 42 page TIMING INFORMATION N+1 Dx_y_P N+2 N+6 t CLKL t DRY t DATA t CLKH t a Dx_y_M CLKP CLKM N+3 N+4 N+5 DRY_M DRY_P Sample N T0158-02 Latency = 4.5 Clock Cycles CLK Input CLK Output Output Data O O O O O O O O E E E E E E E N+1 N N–1 N–2 N–3 N–4 N–5 E=EvenBits=B0,B2,B4,B6,B8,B10,B12,B14 O =OddBits=B1,B3,B5,B7,B9,B11,B13,B15 TIMING CHARACTERISTICS (1) ADS5481 ADS5482 ADS5483 www.ti.com................................................................................................................................................... SLAS565A – JUNE 2008 – REVISED NOVEMBER 2008 Figure 1. Timing Diagram Typical values at TA = +25°C: minimum and maximum values over full temperature range TMIN = –40°C to TMAX = +85°C, sampling rate = max rated, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 3-VPP differential clock, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ta Aperture delay 200 ps Aperture jitter, rms Internal jitter of the ADC 80 fs Latency 4.5 cycles tCLK Clock period 1e9/CLK 100 ns tCLKH Clock pulse duration, high CLK = max rated clock for that part number 0.5e9/CLK 50 ns tCLKL Clock pulse duration, low 0.5e9/CLK 50 ns tDRY CLK to DRY delay(2) 800 1250 1700 ps Zero crossing, 5-pF parasitic to GND tDATA CLK to DATA delay(2) 700 1250 1800 ps tSKEW DATA to DRY skew tDATA – tDRY, 5-pF parasitic to GND –600 0 600 ps tRISE DRY/DATA rise time 500 ps 5-pF parasitic to GND tFALL DRY/DATA fall time 500 ps (1) Timing parameters are assured by design or characterization, but not production tested. (2) DRY and DATA are updated on the rising edge of CLK input. The latency must be added to tDATA to determine the overall propagation delay. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): ADS5481 ADS5482 ADS5483 |
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