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ADV7181CBSTZ-REEL Arkusz danych(PDF) 6 Page - Analog Devices |
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ADV7181CBSTZ-REEL Arkusz danych(HTML) 6 Page - Analog Devices |
6 / 20 page ADV7181C Rev. 0 | Page 6 of 20 TIMING CHARACTERISTICS AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. TMIN to TMAX = −40°C to +85°C, unless otherwise noted. Table 3. Parameter1, 2 Symbol Test Conditions Min Typ Max Unit SYSTEM CLOCK AND CRYSTAL Crystal Nominal Frequency 28.63636 MHz Crystal Frequency Stability ±50 ppm LLC Frequency Range3 12.825 110 MHz I2C PORT4 SCLK Frequency 400 kHz SCLK Min Pulse Width High t1 0.6 μs SCLK Min Pulse Width Low t2 1.3 μs Hold Time (Start Condition) t3 0.6 μs Setup Time (Start Condition) t4 0.6 μs SDA Setup Time t5 100 ns SCLK and SDA Rise Time t6 300 ns SCLK and SDA Fall Time t7 300 ns Setup Time for Stop Condition t8 0.6 μs RESET FEATURE Reset Pulse Width 5 ms CLOCK OUTPUTS LLC Mark Space Ratio t9:t10 45:55 55:45 % duty cycle DATA and CONTROL OUTPUTS Data Output Transition Time SDR (SDP)5 t11 Negative clock edge to start of valid data 3.6 ns Data Output Transition Time SDR (SDP)5 t12 End of valid data to negative clock edge 2.4 ns Data Output Transition Time SDR (CP)6 t13 End of valid data to negative clock edge 2.8 ns Data Output Transition Time SDR (CP)6 t14 Negative clock edge to start of valid data 0.1 ns Data Output Transition Time DDR (CP)6, 7 t15 Positive clock edge to end of valid data −4 + TLLC/4 ns Data Output Transition Time DDR (CP)6, 7 t16 Positive clock edge to start of valid data 0.25 + TLLC/4 ns Data Output Transition Time DDR (CP)6, 7 t17 Negative clock edge to end of valid data −2.95 + TLLC/4 ns Data Output Transition Time DDR (CP)6, 7 t18 Negative clock edge to start of valid data −0.5 + TLLC/4 ns 1 The minimum/maximum specifications are guaranteed over this range. 2 Guaranteed by characterization. 3 Maximum LLC frequency is 110 MHz. 4 TTL input values are 0 V to 3 V, with rise/fall times of ≤3 ns, measured between the 10% and 90% points. 5 SDP timing figures obtained using default drive strength value (0xD5) in Register Subaddress 0xF4. 6 CP timing figures obtained using maximum drive strength value (0xFF) in Register Subaddress 0xF4. 7 DDR timing specifications dependent on LLC output pixel clock; TLCC/4 = 9.25 ns at LLC = 27 MHz. |
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