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ADXL345BCCZ-RL1 Datasheet(Arkusz danych) 9 Page - Analog Devices

Numer części ADXL345BCCZ-RL1
Szczegółowy opis  Three-Axis, ±2/4/8/16g Digital Accelerometer
Pobierz  24 Pages
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
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 9 page
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Preliminary Technical Data
ADXL345
Rev. PrA | Page 9 of 24
SERIAL COMMUNICATIONS
I2C and SPI digital communications are available. In both cases,
the ADXL345 operates as a slave. I2C mode is enabled if the CS
pin is tied high to VDD I/O. In SPI mode, the CS pin is controlled
by the bus master. In both SPI and I2C modes of operation, data
transmitted from the ADXL345 to the master device should be
ignored during writes to the ADXL345.
SPI
For SPI, either 3-wire or 4-wire configuration is possible, as
shown in the connection diagrams in Figure 3 and Figure 4.
Clearing the SPI bit in the DATA_FORMAT register selects 4-wire
mode while setting the SPI bit selects 3-wire mode. The maximum
SPI clock speed is 5 MHz, with 12 pF maximum loading and
the timing scheme follows CPOL = 1, CPHA = 1.
Figure 3. 4-Wire SPI connection
CS is the serial port enable line, and is controlled by the SPI
master. It must go low at the start of transmissions and back
Figure 4. 3-Wire SPI connection
high at the end as shown in Figure 5. SCLK is the serial port
clock and is supplied by the SPI master. It is stopped high when
CS is high, during period of no transmission. SDI and SDO are
the serial data in and out respectively. Data should be sampled
at the rising edge of SCLK.
To read or write multiple bytes in a single transmission, the
Multi-Byte bit, located after the R/W bit in the first byte
transfer, must be set. After the register addressing and the first
byte of data, continued clock pulses will cause the ADXL345 to
point to the next register for read or write. Continued clock
pulses will continue to shift the register that is pointed to until
the clock pulses are ceased and CS is de-asserted. To perform
reads or writes on different, non-sequential registers, CS must
be de-asserted between transmissions and the new register must
be addressed separately.
The timing diagram for 3-wire SPI reads or writes is shown in
Figure 5. The 4-wire equivalents for SPI reads and writes are
shown in Figure 6 and Figure 7 respectively.
CS
SCLK
SDI
SDO
R/W
MB
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
D[6]
D[7]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
tDELAY
tSCLK
tS
tM
tQUIET
tSETUP
tHOLD
tSDO
CS
SCLK
SDI
SDO
R/W
MB
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
D[6]
D[7]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
tDELAY
tSCLK
tS
tM
tQUIET
tSETUP
tHOLD
tSDO
Figure 5. SPI 3-wire Timing Diagram
CS
SCLK
SDI
SDO
R/W
MB
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
D[6]
D[7]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
tDELAY
tSCLK
tS
tM
tQUIET
tSETUP
tHOLD
tSDO
CS
SCLK
SDI
SDO
R/W
MB
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
D[6]
D[7]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
tDELAY
tSCLK
tS
tM
tQUIET
tSETUP
tHOLD
tSDO
R/W
MB
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
D[6]
D[7]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
tDELAY
tSCLK
tS
tM
tQUIET
tSETUP
tHOLD
tSDO
Figure 6. SPI 4-wire Read Timing Diagram
ADXL345
PROCESSOR
CS
D OUT
SDA/SDI/SDIO
D IN/OUT
SDO
SCL/SCLK
D OUT
ADXL345
PROCESSOR
D OUT
SDA/SDI/SDIO
D IN/OUT
SDO
D IN
SCL/SCLK
D OUT
CS




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