ADXL345BCCZ-RL71 datasheet(17/24 Pages) AD

Numer części	ADXL345BCCZ-RL71

Szczegółowy opis	Three-Axis, 짹2/4/8/16g Digital Accelerometer

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Producent	AD [Analog Devices]

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Preliminary Technical Data

ADXL345

Rev. PrA | Page 17 of 24

SPI: A value of ‘1’ sets the device to 3-wire SPI and a value of ‘0’

sets the device to 4-wire SPI.

INT_INVERT: A value of ‘0’ sets the interrupts to Active High

while a value of ‘1’ sets the interrupts to Active Low.

FULL_RES: When this bit is set with a value of ‘1’ the device is

in Full-Resolution Mode, where the output resolution increases

with RANGE to maintain a 4 m

g/LSB scale factor. When this

bit is ’0’ the device is in 10-bit Mode and RANGE determine the

maximum g-Range and scale factor.

JUSTIFY: A ‘1’ = Left (MSB) justified and a ‘0’ = Right justified

with sign extension.

RANGE: Sets the g-Range based on Table 14 below.

Table 14. g-Range Setting

D1

D0

g-Range

0

±2 g

0

1

±4 g

1

0

±8 g

1

±16 g

0x32, 0x33 DATAX0, DATAX1 (read only)

D7

D6

D5

D4

D3

D2

D1

D0

0x34, 0x35 DATAY0, DATAY1 (read only)

D7

D6

D5

D4

D3

D2

D1

D0

0x36, 0x37 DATAZ0, DATAZ1 (read only)

D7

D6

D5

D4

D3

D2

D1

D0

These six bytes hold the output data for each axis. The output

data is two’s complement with DATAx0 as the LSByte and

DATAx1 as the MSByte. The DATA_FORMAT register (0x31)

controls the format of the data. It is recommended that a burst

read of all of the registers is performed to prevent the change of

data between reads of sequential registers.

0x38 FIFO_CTL (read/write)

D7

D6

D5

D4

D3

D2

D1

D0

TRIGGER

FIFO_MODE

SAMPLES

FIFO_MODE: Corresponds to the FIFO Mode as shown in

Table 15 below.

TRIGGER: A value of ‘0’ sets the trigger event of Trigger Mode

to INT1 and a value of ‘1’ sets the trigger event to INT2.

SAMPLES: Function depends on the FIFO Mode as shown in

Table 16 below. Entering a value of zero in SAMPLES will

immediately set the WATERMARK status bit in

INT_SOURCE, regardless of FIFO mode. Undesirable

operation may occur if a value of zero is used for SAMPLES

when Trigger Mode is used.

Table 15. FIFO Modes

D7 D6 MODE Function

0

0 Bypass

The FIFO is bypassed

0

1 FIFO

FIFO collects up to 32 values then

stops collecting data

1

0 Stream

FIFO holds the last 32 data values.

Once full, the FIFO’s oldest data is

lost as it is replaced with newer data

1

1 Trigger When triggered by the TRIGGER the

FIFO holds the last 32 data values and

stops when full.

Table 16. SAMPLES Functions

FIFO Mode Samples Function

Bypass

None

FIFO

Specifies how many FIFO entries are need to trigger

a Watermark interrupt

Stream

Specifies how many FIFO entries are need to trigger

a Watermark interrupt

Trigger

Specifies how many FIFO samples before the trigger

event are retained in the FIFO buffer

0x39 FIFO_STATUS (read)

D7

D6

D5

D4

D3

D2

D1

D0

FIFO_TRIG

X

ENTRIES

FIFO_TRIG: A ‘1’ corresponds to a trigger event occurring

while a ‘0’ means that a FIFO trigger event has not yet occurred.

ENTRIES: Reports how many data values are stored in the

FIFO. To collect the data from the FIFO, access is through the

standard DATAX, DATAY, and DATAZ registers. FIFO reads

must be done in burst, or multi-byte, mode as each FIFO level is

cleared after any read, single- or multi-byte, of the FIFO. The

FIFO stores a maximum of 32 entries, which equates to a

maximum of 33 entries available at any given time, due to the

fact that an additional entry is available at the output filter of

device.

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