DEVICE INFORMATION

REF

IN

REF

OUT

AGND

AV

DD

DB11

DB10

DB9

DB8

BV

DD

BGND

WR

RD

CS

CLOCK

CONVST

BUSY

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

32

9

31

10

30

11

29

12

28

13

27

14

26

15

25

16

ADS7865

PBS PACKAGE

TQFP-32

(TOP VIEW)

TERMINAL FUNCTIONS

PIN NUMBER

NAME

DESCRIPTION

1

Reference voltage input. A ceramic capacitor of 470nF (min) is required at this terminal.

2

Reference voltage output. The programmable internal voltage reference output is available on this pin.

3

AGND

Analog ground. Connect to analog ground plane.

4

Analog power supply, 2.7V to 5.5V. Decouple to AGND with a 1

µF ceramic capacitor.

5

DB11

Data bit 11, MSB

6

DB10

Data bit 10

7

DB9

Data bit 9

8

DB8

Data bit 8

9

DB7

Data bit 7

10

DB6

Data bit 6

11

DB5

Data bit 5

12

DB4

Data bit 4

13

DB3

Data bit 3

14

DB2

Data bit 2

15

DB1

Data bit 1

16

DB0

Data bit 0

ADC busy indicator. BUSY goes high when the inputs are in hold mode and returns to low after the

17

BUSY

conversion has been finished.

Conversion start. The ADC switches from the sample into the hold mode on the falling edge of

18

CONVST

CONVST, independent of the status of the CLOCK. The conversion itself starts with the next rising

edge of CLOCK.

19

CLOCK

External clock input.

Chip select. When low, the parallel interface of the device is active; when high, input signals are

20

CS

ignored and output signals are 3-state.

Read data. Falling edge active synchronization pulse for the parallel data outputs. RD only triggers,

21

RD

when CS is low.

22

WR

Write data. Rising edge latches in the parallel data inputs. WR only triggers, when CS is low.

6

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